Hardware
/
litex
mirror of https://github.com/enjoy-digital/litex.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

gen: integrate migen changes

This commit is contained in:
Florent Kermarrec 2018-12-04 21:06:51 +01:00
parent 96527b5a3a
commit bf3b4eec34
2 changed files with 3 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
litex/gen/fhdl/verilog.py
View File

@ -377,8 +377,8 @@ def convert(f, ios=None, name="top",
f = lower_complex_slices(f)
insert_resets(f)
f = lower_basics(f)
fs, lowered_specials = lower_specials(special_overrides, f.specials)
f += lower_basics(fs)
f, lowered_specials = lower_specials(special_overrides, f)
f = lower_basics(f)
for io in sorted(ios, key=lambda x: x.duid):
if io.name_override is None:

4
litex/gen/sim/core.py
View File

@ -250,9 +250,7 @@ class Simulator:
overrides = {AsyncResetSynchronizer: DummyAsyncResetSynchronizer}
overrides.update(special_overrides)
fs, lowered = lower_specials(overrides=overrides, specials=self.fragment.specials)
self.fragment += fs
self.fragment.specials -= lowered
f, lowered = lower_specials(overrides, self.fragment)
if self.fragment.specials:
raise ValueError("Could not lower all specials", self.fragment.specials)