mirror of
https://github.com/enjoy-digital/litex.git
synced 2025-01-04 09:52:26 -05:00
pytholite: move expression and register handling to separate modules
This commit is contained in:
Sebastien Bourdeauducq
parent
f59fd69e34
commit
bf5ce8dc20
3 changed files with 169 additions and 152 deletions
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@ -1,62 +1,14 @@
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import inspect
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import ast
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from operator import itemgetter
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from migen.fhdl.structure import *
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from migen.fhdl.structure import _Slice
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from migen.fhdl import visit as fhdl
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from migen.pytholite.reg import *
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from migen.pytholite.expr import *
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from migen.pytholite import transel
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from migen.pytholite.io import make_io_object, gen_io
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from migen.pytholite.fsm import *
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class FinalizeError(Exception):
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pass
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class _AbstractLoad:
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def __init__(self, target, source):
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self.target = target
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self.source = source
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def lower(self):
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if not self.target.finalized:
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raise FinalizeError
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return self.target.sel.eq(self.target.source_encoding[self.source])
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class _LowerAbstractLoad(fhdl.NodeTransformer):
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def visit_unknown(self, node):
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if isinstance(node, _AbstractLoad):
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return node.lower()
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else:
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return node
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class _Register:
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def __init__(self, name, nbits):
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self.name = name
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self.storage = Signal(BV(nbits), name=self.name)
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self.source_encoding = {}
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self.finalized = False
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def load(self, source):
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if source not in self.source_encoding:
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self.source_encoding[source] = len(self.source_encoding) + 1
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return _AbstractLoad(self, source)
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def finalize(self):
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if self.finalized:
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raise FinalizeError
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self.sel = Signal(BV(bits_for(len(self.source_encoding) + 1)), name="pl_regsel_"+self.name)
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self.finalized = True
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def get_fragment(self):
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if not self.finalized:
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raise FinalizeError
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# do nothing when sel == 0
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items = sorted(self.source_encoding.items(), key=itemgetter(1))
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cases = [(Constant(v, self.sel.bv),
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self.storage.eq(k)) for k, v in items]
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sync = [Case(self.sel, *cases)]
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return Fragment(sync=sync)
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def _is_name_used(node, name):
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for n in ast.walk(node):
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if isinstance(n, ast.Name) and n.id == name:
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@ -68,6 +20,7 @@ class _Compiler:
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self.ioo = ioo
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self.symdict = symdict
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self.registers = registers
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self.ec = ExprCompiler(self.symdict)
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def visit_top(self, node):
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if isinstance(node, ast.Module) \
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@ -109,12 +62,15 @@ class _Compiler:
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def visit_assign(self, sa, node, statements):
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if isinstance(node.value, ast.Call):
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is_special = False
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try:
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value = self.visit_expr_call(node.value)
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value = self.ec.visit_expr_call(node.value)
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except NotImplementedError:
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is_special = True
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if is_special:
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return self.visit_assign_special(sa, node, statements)
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else:
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value = self.visit_expr(node.value)
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value = self.ec.visit_expr(node.value)
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if isinstance(value, Value):
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r = []
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for target in node.targets:
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@ -146,7 +102,7 @@ class _Compiler:
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targetname = node.targets[0].id
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else:
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targetname = "unk"
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reg = _Register(targetname, nbits)
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reg = ImplRegister(targetname, nbits)
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self.registers.append(reg)
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for target in node.targets:
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if isinstance(target, ast.Name):
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@ -173,6 +129,7 @@ class _Compiler:
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or not isinstance(ystatement.value, ast.Yield) \
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or not isinstance(ystatement.value.value, ast.Name) \
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or ystatement.value.value.id != modelname:
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print(ast.dump(ystatement))
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raise NotImplementedError("Unrecognized I/O pattern")
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# following optional statements are assignments to registers
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@ -202,7 +159,7 @@ class _Compiler:
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return fstatement
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def visit_if(self, sa, node):
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test = self.visit_expr(node.test)
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test = self.ec.visit_expr(node.test)
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states_t, exit_states_t = self.visit_block(node.body)
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states_f, exit_states_f = self.visit_block(node.orelse)
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exit_states = exit_states_t + exit_states_f
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@ -218,7 +175,7 @@ class _Compiler:
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exit_states)
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def visit_while(self, sa, node):
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test = self.visit_expr(node.test)
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test = self.ec.visit_expr(node.test)
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states_b, exit_states_b = self.visit_block(node.body)
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test_state = [If(test, AbstractNextState(states_b[0]))]
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@ -269,102 +226,6 @@ class _Compiler:
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sa.assemble(states, exit_states)
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else:
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raise NotImplementedError
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# expressions
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def visit_expr(self, node):
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if isinstance(node, ast.Call):
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return self.visit_expr_call(node)
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elif isinstance(node, ast.BinOp):
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return self.visit_expr_binop(node)
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elif isinstance(node, ast.Compare):
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return self.visit_expr_compare(node)
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elif isinstance(node, ast.Name):
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return self.visit_expr_name(node)
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elif isinstance(node, ast.Num):
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return self.visit_expr_num(node)
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else:
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raise NotImplementedError
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def visit_expr_call(self, node):
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if isinstance(node.func, ast.Name):
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callee = self.symdict[node.func.id]
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else:
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raise NotImplementedError
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if callee == transel.bitslice:
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if len(node.args) != 2 and len(node.args) != 3:
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raise TypeError("bitslice() takes 2 or 3 arguments")
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val = self.visit_expr(node.args[0])
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low = ast.literal_eval(node.args[1])
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if len(node.args) == 3:
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up = ast.literal_eval(node.args[2])
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else:
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up = low + 1
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return _Slice(val, low, up)
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else:
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raise NotImplementedError
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def visit_expr_binop(self, node):
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left = self.visit_expr(node.left)
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right = self.visit_expr(node.right)
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if isinstance(node.op, ast.Add):
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return left + right
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elif isinstance(node.op, ast.Sub):
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return left - right
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elif isinstance(node.op, ast.Mult):
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return left * right
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elif isinstance(node.op, ast.LShift):
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return left << right
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elif isinstance(node.op, ast.RShift):
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return left >> right
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elif isinstance(node.op, ast.BitOr):
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return left | right
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elif isinstance(node.op, ast.BitXor):
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return left ^ right
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elif isinstance(node.op, ast.BitAnd):
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return left & right
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else:
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raise NotImplementedError
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def visit_expr_compare(self, node):
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test = self.visit_expr(node.left)
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r = None
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for op, rcomparator in zip(node.ops, node.comparators):
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comparator = self.visit_expr(rcomparator)
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if isinstance(op, ast.Eq):
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comparison = test == comparator
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elif isinstance(op, ast.NotEq):
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comparison = test != comparator
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elif isinstance(op, ast.Lt):
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comparison = test < comparator
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elif isinstance(op, ast.LtE):
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comparison = test <= comparator
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elif isinstance(op, ast.Gt):
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comparison = test > comparator
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elif isinstance(op, ast.GtE):
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comparison = test >= comparator
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else:
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raise NotImplementedError
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if r is None:
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r = comparison
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else:
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r = r & comparison
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test = comparator
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return r
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def visit_expr_name(self, node):
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if node.id == "True":
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return Constant(1)
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if node.id == "False":
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return Constant(0)
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r = self.symdict[node.id]
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if isinstance(r, _Register):
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r = r.storage
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if isinstance(r, int):
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r = Constant(r)
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return r
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def visit_expr_num(self, node):
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return Constant(node.n)
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def make_pytholite(func, **ioresources):
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ioo = make_io_object(**ioresources)
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@ -381,7 +242,7 @@ def make_pytholite(func, **ioresources):
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regf += register.get_fragment()
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fsm = implement_fsm(states)
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fsmf = _LowerAbstractLoad().visit(fsm.get_fragment())
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fsmf = LowerAbstractLoad().visit(fsm.get_fragment())
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ioo.fragment = regf + fsmf
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return ioo
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104
migen/pytholite/expr.py
Normal file
104
migen/pytholite/expr.py
Normal file
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@ -0,0 +1,104 @@
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import ast
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from migen.fhdl.structure import *
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from migen.pytholite import transel
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from migen.pytholite.reg import *
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class ExprCompiler:
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def __init__(self, symdict):
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self.symdict = symdict
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def visit_expr(self, node):
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if isinstance(node, ast.Call):
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return self.visit_expr_call(node)
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elif isinstance(node, ast.BinOp):
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return self.visit_expr_binop(node)
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elif isinstance(node, ast.Compare):
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return self.visit_expr_compare(node)
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elif isinstance(node, ast.Name):
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return self.visit_expr_name(node)
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elif isinstance(node, ast.Num):
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return self.visit_expr_num(node)
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else:
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raise NotImplementedError
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def visit_expr_call(self, node):
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if isinstance(node.func, ast.Name):
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callee = self.symdict[node.func.id]
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else:
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raise NotImplementedError
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if callee == transel.bitslice:
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if len(node.args) != 2 and len(node.args) != 3:
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raise TypeError("bitslice() takes 2 or 3 arguments")
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val = self.visit_expr(node.args[0])
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low = ast.literal_eval(node.args[1])
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if len(node.args) == 3:
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up = ast.literal_eval(node.args[2])
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else:
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up = low + 1
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return _Slice(val, low, up)
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else:
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raise NotImplementedError
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def visit_expr_binop(self, node):
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left = self.visit_expr(node.left)
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right = self.visit_expr(node.right)
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if isinstance(node.op, ast.Add):
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return left + right
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elif isinstance(node.op, ast.Sub):
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return left - right
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elif isinstance(node.op, ast.Mult):
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return left * right
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elif isinstance(node.op, ast.LShift):
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return left << right
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elif isinstance(node.op, ast.RShift):
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return left >> right
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elif isinstance(node.op, ast.BitOr):
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return left | right
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elif isinstance(node.op, ast.BitXor):
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return left ^ right
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elif isinstance(node.op, ast.BitAnd):
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return left & right
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else:
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raise NotImplementedError
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def visit_expr_compare(self, node):
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test = self.visit_expr(node.left)
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r = None
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for op, rcomparator in zip(node.ops, node.comparators):
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comparator = self.visit_expr(rcomparator)
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if isinstance(op, ast.Eq):
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comparison = test == comparator
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elif isinstance(op, ast.NotEq):
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comparison = test != comparator
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elif isinstance(op, ast.Lt):
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comparison = test < comparator
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elif isinstance(op, ast.LtE):
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comparison = test <= comparator
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elif isinstance(op, ast.Gt):
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comparison = test > comparator
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elif isinstance(op, ast.GtE):
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comparison = test >= comparator
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else:
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raise NotImplementedError
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if r is None:
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r = comparison
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else:
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r = r & comparison
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test = comparator
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return r
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def visit_expr_name(self, node):
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if node.id == "True":
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return Constant(1)
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if node.id == "False":
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return Constant(0)
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r = self.symdict[node.id]
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if isinstance(r, ImplRegister):
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r = r.storage
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if isinstance(r, int):
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r = Constant(r)
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return r
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def visit_expr_num(self, node):
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return Constant(node.n)
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52
migen/pytholite/reg.py
Normal file
52
migen/pytholite/reg.py
Normal file
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@ -0,0 +1,52 @@
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from operator import itemgetter
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from migen.fhdl.structure import *
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from migen.fhdl import visit as fhdl
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class FinalizeError(Exception):
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pass
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class AbstractLoad:
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def __init__(self, target, source):
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self.target = target
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self.source = source
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def lower(self):
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if not self.target.finalized:
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raise FinalizeError
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return self.target.sel.eq(self.target.source_encoding[self.source])
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class LowerAbstractLoad(fhdl.NodeTransformer):
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def visit_unknown(self, node):
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if isinstance(node, AbstractLoad):
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return node.lower()
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else:
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return node
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class ImplRegister:
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def __init__(self, name, nbits):
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self.name = name
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self.storage = Signal(BV(nbits), name=self.name)
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self.source_encoding = {}
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self.finalized = False
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def load(self, source):
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if source not in self.source_encoding:
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self.source_encoding[source] = len(self.source_encoding) + 1
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return AbstractLoad(self, source)
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def finalize(self):
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if self.finalized:
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raise FinalizeError
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self.sel = Signal(BV(bits_for(len(self.source_encoding) + 1)), name="pl_regsel_"+self.name)
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self.finalized = True
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def get_fragment(self):
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if not self.finalized:
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raise FinalizeError
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# do nothing when sel == 0
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items = sorted(self.source_encoding.items(), key=itemgetter(1))
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cases = [(Constant(v, self.sel.bv),
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self.storage.eq(k)) for k, v in items]
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sync = [Case(self.sel, *cases)]
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return Fragment(sync=sync)
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