mirror of
https://github.com/enjoy-digital/litex.git
synced 2025-01-04 09:52:26 -05:00
Fix memory transducer bug, --with-sdram for BIOS works, memspeed works
This commit is contained in:
sadullah
parent
cf01ea65f3
commit
bf864d335b
8 changed files with 139 additions and 513 deletions
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@ -46,11 +46,11 @@ class BaseSoC(SoCCore):
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# SoCCore ----------------------------------------------------------------------------------
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SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
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sys_clk_freq = int(50e6)
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# sys_clk_freq = int(50e6)
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = _CRG(platform, sys_clk_freq)
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self.add_constant("UART_POLLING",None)
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# self.add_constant("UART_POLLING",None)
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# DDR3 SDRAM -------------------------------------------------------------------------------
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if not self.integrated_main_ram_size:
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self.submodules.ddrphy = s7ddrphy.K7DDRPHY(platform.request("ddram"),
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@ -1,434 +0,0 @@
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/**
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*
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* ExampleBlackParrotSystem For Simulating With Litex
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*
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*/
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`include "bsg_noc_links.vh"
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module ExampleBlackParrotSystem
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import bp_common_pkg::*;
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import bp_common_aviary_pkg::*;
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import bp_be_pkg::*;
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import bp_common_rv64_pkg::*;
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import bp_cce_pkg::*;
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import bp_cfg_link_pkg::*;
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#(parameter bp_cfg_e cfg_p = e_bp_single_core_cfg // Replaced by the flow with a specific bp_cfg
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`declare_bp_proc_params(cfg_p)
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`declare_bp_me_if_widths(paddr_width_p, cce_block_width_p, num_lce_p, lce_assoc_p)
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// Tracing parameters
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, parameter calc_trace_p = 1
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, parameter cce_trace_p = 0
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, parameter cmt_trace_p = 0
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, parameter dram_trace_p = 0
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, parameter skip_init_p = 0
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, parameter mem_load_p = 1
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, parameter mem_file_p = "prog.mem"
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, parameter mem_cap_in_bytes_p = 2**20
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, parameter [paddr_width_p-1:0] mem_offset_p = paddr_width_p'(32'h8000_0000)
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)
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(input clk_i
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, input reset_i
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//Wishbone interface
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, input [63:0] wbm_dat_i
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, output [63:0] wbm_dat_o
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, input wbm_ack_i
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// , input wbm_err_i
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// , input wbm_rty_i
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, output [36:0] wbm_adr_o //TODO parametrize this
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, output wbm_stb_o
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, output wbm_cyc_o
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, output wbm_sel_o //TODO: how many bits ? check 3.5 table 3-1
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, output wbm_we_o
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, output [2:0] wbm_cti_o //TODO: hardwire in Litex
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, output [1:0] wbm_bte_o //TODO: hardwire in Litex
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, output all_finished_debug_o //SC_add
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, output core_passed_debug
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, output core_failed_debug
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, input [3:0] interrupts
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);
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`declare_bsg_ready_and_link_sif_s(mem_noc_flit_width_p, bsg_ready_and_link_sif_s);
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`declare_bp_me_if(paddr_width_p, cce_block_width_p, num_lce_p, lce_assoc_p)
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bsg_ready_and_link_sif_s cmd_link_li, cmd_link_lo;
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bsg_ready_and_link_sif_s resp_link_li, resp_link_lo;
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bsg_ready_and_link_sif_s mem_cmd_link_li, mem_cmd_link_lo, mem_resp_link_li, mem_resp_link_lo;
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bsg_ready_and_link_sif_s cfg_cmd_link_li, cfg_cmd_link_lo, cfg_resp_link_li, cfg_resp_link_lo;
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assign mem_cmd_link_li = cmd_link_li;
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assign cfg_cmd_link_li = '{ready_and_rev: cmd_link_li.ready_and_rev, default: '0};
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assign cmd_link_lo = '{data: cfg_cmd_link_lo.data
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,v : cfg_cmd_link_lo.v
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,ready_and_rev: mem_cmd_link_lo.ready_and_rev
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};
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assign mem_resp_link_li = '{ready_and_rev: resp_link_li.ready_and_rev, default: '0};
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assign cfg_resp_link_li = resp_link_li;
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assign resp_link_lo = '{data: mem_resp_link_lo.data
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,v : mem_resp_link_lo.v
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,ready_and_rev: cfg_resp_link_lo.ready_and_rev
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};
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bp_cce_mem_msg_s mem_resp_li;
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logic mem_resp_v_li, mem_resp_ready_lo;
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bp_cce_mem_msg_s mem_cmd_lo;
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logic mem_cmd_v_lo, mem_cmd_yumi_li;
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bp_cce_mem_msg_s dram_resp_lo;
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logic dram_resp_v_lo, dram_resp_ready_li;
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bp_cce_mem_msg_s dram_cmd_li;
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logic dram_cmd_v_li, dram_cmd_yumi_lo;
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bp_cce_mem_msg_s host_resp_lo;
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logic host_resp_v_lo, host_resp_ready_li;
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bp_cce_mem_msg_s host_cmd_li;
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logic host_cmd_v_li, host_cmd_yumi_lo;
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bp_cce_mem_msg_s cfg_cmd_lo;
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logic cfg_cmd_v_lo, cfg_cmd_ready_li;
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bp_cce_mem_msg_s cfg_resp_li;
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logic cfg_resp_v_li, cfg_resp_ready_lo;
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logic [mem_noc_cord_width_p-1:0] dram_cord_lo, mmio_cord_lo, host_cord_lo;
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logic [num_core_p-1:0][mem_noc_cord_width_p-1:0] tile_cord_lo;
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logic [num_mem_p-1:0][mem_noc_cord_width_p-1:0] mem_cord_lo;
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assign mmio_cord_lo[0+:mem_noc_x_cord_width_p] = mmio_x_pos_p;
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assign mmio_cord_lo[mem_noc_x_cord_width_p+:mem_noc_y_cord_width_p] = '0;
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assign dram_cord_lo[0+:mem_noc_x_cord_width_p] = mem_noc_x_dim_p+2;
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assign dram_cord_lo[mem_noc_x_cord_width_p+:mem_noc_y_cord_width_p] = '0;
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assign host_cord_lo[0+:mem_noc_x_cord_width_p] = mem_noc_x_dim_p+2;
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assign host_cord_lo[mem_noc_x_cord_width_p+:mem_noc_y_cord_width_p] = '0;
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for (genvar j = 0; j < mem_noc_y_dim_p; j++)
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begin : y
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for (genvar i = 0; i < mem_noc_x_dim_p; i++)
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begin : x
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localparam idx = j*mem_noc_x_dim_p + i;
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assign tile_cord_lo[idx][0+:mem_noc_x_cord_width_p] = i+1;
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assign tile_cord_lo[idx][mem_noc_x_cord_width_p+:mem_noc_y_cord_width_p] = j+1;
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end
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end
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for (genvar i = 0; i < num_mem_p; i++)
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begin : x
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assign mem_cord_lo[i][0+:mem_noc_x_cord_width_p] = i;
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assign mem_cord_lo[i][mem_noc_x_cord_width_p+:mem_noc_y_cord_width_p] = '0;
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end
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// Chip
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bp_chip
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#(.cfg_p(cfg_p))
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chip
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(.core_clk_i(clk_i)
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,.core_reset_i(reset_i)
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,.coh_clk_i(clk_i)
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,.coh_reset_i(reset_i)
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,.mem_clk_i(clk_i)
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,.mem_reset_i(reset_i)
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,.mem_cord_i(mem_cord_lo)
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,.tile_cord_i(tile_cord_lo)
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,.dram_cord_i(dram_cord_lo)
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,.mmio_cord_i(mmio_cord_lo)
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,.host_cord_i(host_cord_lo)
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,.prev_cmd_link_i('0)
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,.prev_cmd_link_o()
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,.prev_resp_link_i('0)
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,.prev_resp_link_o()
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,.next_cmd_link_i(cmd_link_lo)
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,.next_cmd_link_o(cmd_link_li)
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,.next_resp_link_i(resp_link_lo)
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,.next_resp_link_o(resp_link_li)
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);
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bind bp_be_top
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bp_nonsynth_commit_tracer
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#(.cfg_p(cfg_p))
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commit_tracer
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(.clk_i(clk_i & (ExampleBlackParrotSystem.cmt_trace_p == 1))
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,.reset_i(reset_i)
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,.mhartid_i('0)
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,.commit_v_i(be_calculator.instret_mem3_o)
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,.commit_pc_i(be_calculator.pc_mem3_o)
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,.commit_instr_i(be_calculator.instr_mem3_o)
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,.rd_w_v_i(be_calculator.int_regfile.rd_w_v_i)
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,.rd_addr_i(be_calculator.int_regfile.rd_addr_i)
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,.rd_data_i(be_calculator.int_regfile.rd_data_i)
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);
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/* bind bp_be_top
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bp_be_nonsynth_tracer
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#(.cfg_p(cfg_p))
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tracer
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// Workaround for verilator binding by accident
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// TODO: Figure out why tracing is always enabled
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(.clk_i(clk_i & (ExampleBlackParrotSystem.calc_trace_p == 1))
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,.reset_i(reset_i)
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,.mhartid_i(be_calculator.proc_cfg.core_id)
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,.issue_pkt_i(be_calculator.issue_pkt)
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,.issue_pkt_v_i(be_calculator.issue_pkt_v_i)
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,.fe_nop_v_i(be_calculator.fe_nop_v)
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,.be_nop_v_i(be_calculator.be_nop_v)
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,.me_nop_v_i(be_calculator.me_nop_v)
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,.dispatch_pkt_i(be_calculator.dispatch_pkt)
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,.ex1_br_tgt_i(be_calculator.calc_status.int1_br_tgt)
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,.ex1_btaken_i(be_calculator.calc_status.int1_btaken)
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,.iwb_result_i(be_calculator.comp_stage_n[3])
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,.fwb_result_i(be_calculator.comp_stage_n[4])
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,.cmt_trace_exc_i(be_calculator.exc_stage_n[1+:5])
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,.trap_v_i(be_mem.csr.trap_v_o)
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,.mtvec_i(be_mem.csr.mtvec_n)
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,.mtval_i(be_mem.csr.mtval_n[0+:vaddr_width_p])
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,.ret_v_i(be_mem.csr.ret_v_o)
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,.mepc_i(be_mem.csr.mepc_n[0+:vaddr_width_p])
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,.mcause_i(be_mem.csr.mcause_n)
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,.priv_mode_i(be_mem.csr.priv_mode_n)
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,.mpp_i(be_mem.csr.mstatus_n.mpp)
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);
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*/
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/*bind bp_be_top
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bp_be_nonsynth_perf
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#(.cfg_p(cfg_p))
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perf
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(.clk_i(clk_i)
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,.reset_i(reset_i)
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,.mhartid_i(be_calculator.proc_cfg.core_id)
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,.fe_nop_i(be_calculator.exc_stage_r[2].fe_nop_v)
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,.be_nop_i(be_calculator.exc_stage_r[2].be_nop_v)
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,.me_nop_i(be_calculator.exc_stage_r[2].me_nop_v)
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,.poison_i(be_calculator.exc_stage_r[2].poison_v)
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,.roll_i(be_calculator.exc_stage_r[2].roll_v)
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,.instr_cmt_i(be_calculator.calc_status.mem3_cmt_v)
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,.program_finish_i(testbench.program_finish)
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);
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*/
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/*if (dram_trace_p)
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bp_mem_nonsynth_tracer
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#(.cfg_p(cfg_p))
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bp_mem_tracer
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(.clk_i(clk_i & (testbench.dram_trace_p == 1))
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,.reset_i(reset_i)
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,.mem_cmd_i(dram_cmd_li)
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,.mem_cmd_v_i(dram_cmd_v_li)
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,.mem_cmd_yumi_i(dram_cmd_yumi_lo)
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,.mem_resp_i(dram_resp_lo)
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,.mem_resp_v_i(dram_resp_v_lo)
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,.mem_resp_ready_i(dram_resp_ready_li)
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);
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if (cce_trace_p)
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bind bp_cce_top
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bp_cce_nonsynth_tracer
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#(.cfg_p(cfg_p))
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bp_cce_tracer
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(.clk_i(clk_i & (testbench.cce_trace_p == 1))
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,.reset_i(reset_i)
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,.cce_id_i(cce_id_i)
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// To CCE
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,.lce_req_i(lce_req_to_cce)
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,.lce_req_v_i(lce_req_v_to_cce)
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,.lce_req_yumi_i(lce_req_yumi_from_cce)
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,.lce_resp_i(lce_resp_to_cce)
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,.lce_resp_v_i(lce_resp_v_to_cce)
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,.lce_resp_yumi_i(lce_resp_yumi_from_cce)
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// From CCE
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,.lce_cmd_i(lce_cmd_o)
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,.lce_cmd_v_i(lce_cmd_v_o)
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,.lce_cmd_ready_i(lce_cmd_ready_i)
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// To CCE
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,.mem_resp_i(mem_resp_to_cce)
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,.mem_resp_v_i(mem_resp_v_to_cce)
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,.mem_resp_yumi_i(mem_resp_yumi_from_cce)
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// From CCE
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,.mem_cmd_i(mem_cmd_from_cce)
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,.mem_cmd_v_i(mem_cmd_v_from_cce)
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,.mem_cmd_ready_i(mem_cmd_ready_to_cce)
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);
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*/
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// DRAM + link
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bp_me_cce_to_wormhole_link_client
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#(.cfg_p(cfg_p))
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client_link
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(.clk_i(clk_i)
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,.reset_i(reset_i)
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,.mem_cmd_o(mem_cmd_lo)
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,.mem_cmd_v_o(mem_cmd_v_lo)
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,.mem_cmd_yumi_i(mem_cmd_yumi_li)
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,.mem_resp_i(mem_resp_li)
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,.mem_resp_v_i(mem_resp_v_li)
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,.mem_resp_ready_o(mem_resp_ready_lo)
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,.my_cord_i(dram_cord_lo)
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,.my_cid_i(mem_noc_cid_width_p'(0))
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,.cmd_link_i(mem_cmd_link_li)
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,.cmd_link_o(mem_cmd_link_lo)
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,.resp_link_i(mem_resp_link_li)
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,.resp_link_o(mem_resp_link_lo)
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);
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bp2wb_convertor
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#(.cfg_p(cfg_p))
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bp2wb
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(.clk_i(clk_i)
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,.reset_i(reset_i)
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,.mem_cmd_i(dram_cmd_li)
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,.mem_cmd_v_i(dram_cmd_v_li)
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,.mem_cmd_yumi_o(dram_cmd_yumi_lo)
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,.mem_resp_o(dram_resp_lo)
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,.mem_resp_v_o(dram_resp_v_lo)
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,.mem_resp_ready_i(dram_resp_ready_li)
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,.dat_i(wbm_dat_i)
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,.dat_o(wbm_dat_o)
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,.ack_i(wbm_ack_i)
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,.adr_o(wbm_adr_o)
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,.stb_o(wbm_stb_o)
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,.cyc_o(wbm_cyc_o)
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,.sel_o(wbm_sel_o )
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,.we_o(wbm_we_o)
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,.cti_o(wbm_cti_o)
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,.bte_o(wbm_bte_o )
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);
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logic [num_core_p-1:0] program_finish;
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bp_nonsynth_host
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#(.cfg_p(cfg_p))
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host_mmio
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(.clk_i(clk_i)
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,.reset_i(reset_i)
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,.mem_cmd_i(host_cmd_li)
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,.mem_cmd_v_i(host_cmd_v_li)
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,.mem_cmd_yumi_o(host_cmd_yumi_lo)
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,.mem_resp_o(host_resp_lo)
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,.mem_resp_v_o(host_resp_v_lo)
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,.mem_resp_ready_i(host_resp_ready_li)
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,.program_finish_o(program_finish)
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,.all_finished_debug_o(all_finished_debug_o)
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,.core_passed_debug(core_passed_debug)
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,.core_failed_debug(core_failed_debug)
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);
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/*bp_nonsynth_if_verif
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#(.cfg_p(cfg_p))
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if_verif
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();
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*/
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// MMIO arbitration
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// Should this be on its own I/O router?
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logic req_outstanding_r;
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bsg_dff_reset_en
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#(.width_p(1))
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req_outstanding_reg
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(.clk_i(clk_i)
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,.reset_i(reset_i)
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,.en_i(mem_cmd_yumi_li | mem_resp_v_li)
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,.data_i(mem_cmd_yumi_li)
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,.data_o(req_outstanding_r)
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);
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wire host_cmd_not_dram = mem_cmd_v_lo & (mem_cmd_lo.addr < 39'h00_4000_0000 );//dram_base_addr_gp
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assign host_cmd_li = mem_cmd_lo;
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assign host_cmd_v_li = mem_cmd_v_lo & host_cmd_not_dram & ~req_outstanding_r;
|
||||
assign dram_cmd_li = mem_cmd_lo;
|
||||
assign dram_cmd_v_li = mem_cmd_v_lo & ~host_cmd_not_dram & ~req_outstanding_r;
|
||||
assign mem_cmd_yumi_li = host_cmd_not_dram
|
||||
? host_cmd_yumi_lo
|
||||
: dram_cmd_yumi_lo;
|
||||
|
||||
assign mem_resp_li = host_resp_v_lo ? host_resp_lo : dram_resp_lo;
|
||||
assign mem_resp_v_li = host_resp_v_lo | dram_resp_v_lo;
|
||||
assign host_resp_ready_li = mem_resp_ready_lo;
|
||||
assign dram_resp_ready_li = mem_resp_ready_lo;
|
||||
|
||||
// CFG loader + rom + link
|
||||
bp_me_cce_to_wormhole_link_master
|
||||
#(.cfg_p(cfg_p))
|
||||
master_link
|
||||
(.clk_i(clk_i)
|
||||
,.reset_i(reset_i)
|
||||
|
||||
,.mem_cmd_i(cfg_cmd_lo)
|
||||
,.mem_cmd_v_i(cfg_cmd_ready_li & cfg_cmd_v_lo)
|
||||
,.mem_cmd_ready_o(cfg_cmd_ready_li)
|
||||
|
||||
,.mem_resp_o(cfg_resp_li)
|
||||
,.mem_resp_v_o(cfg_resp_v_li)
|
||||
,.mem_resp_yumi_i(cfg_resp_ready_lo & cfg_resp_v_li)
|
||||
|
||||
,.my_cord_i(dram_cord_lo)
|
||||
,.my_cid_i(mem_noc_cid_width_p'(0))
|
||||
,.dram_cord_i(dram_cord_lo)
|
||||
,.mmio_cord_i(mmio_cord_lo)
|
||||
,.host_cord_i(host_cord_lo)
|
||||
|
||||
,.cmd_link_i(cfg_cmd_link_li)
|
||||
,.cmd_link_o(cfg_cmd_link_lo)
|
||||
|
||||
,.resp_link_i(cfg_resp_link_li)
|
||||
,.resp_link_o(cfg_resp_link_lo)
|
||||
);
|
||||
|
||||
localparam cce_instr_ram_addr_width_lp = `BSG_SAFE_CLOG2(num_cce_instr_ram_els_p);
|
||||
bp_cce_mmio_cfg_loader
|
||||
#(.cfg_p(cfg_p)
|
||||
,.inst_width_p(`bp_cce_inst_width)
|
||||
,.inst_ram_addr_width_p(cce_instr_ram_addr_width_lp)
|
||||
,.inst_ram_els_p(num_cce_instr_ram_els_p)
|
||||
,.skip_ram_init_p(skip_init_p)
|
||||
)
|
||||
cfg_loader
|
||||
(.clk_i(clk_i)
|
||||
,.reset_i(reset_i)
|
||||
|
||||
,.mem_cmd_o(cfg_cmd_lo)
|
||||
,.mem_cmd_v_o(cfg_cmd_v_lo)
|
||||
,.mem_cmd_yumi_i(cfg_cmd_ready_li & cfg_cmd_v_lo)
|
||||
|
||||
,.mem_resp_i(cfg_resp_li)
|
||||
,.mem_resp_v_i(cfg_resp_v_li)
|
||||
,.mem_resp_ready_o(cfg_resp_ready_lo)
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
||||
|
|
@ -8,9 +8,9 @@ module bp2wb_convertor
|
|||
import bp_common_aviary_pkg::*;
|
||||
import bp_cce_pkg::*;
|
||||
import bp_me_pkg::*;
|
||||
#(parameter bp_cfg_e cfg_p = e_bp_single_core_cfg
|
||||
`declare_bp_proc_params(cfg_p)
|
||||
`declare_bp_me_if_widths(paddr_width_p, cce_block_width_p, num_lce_p, lce_assoc_p)
|
||||
#(parameter bp_params_e bp_params_p = e_bp_single_core_cfg
|
||||
`declare_bp_proc_params(bp_params_p)
|
||||
`declare_bp_me_if_widths(paddr_width_p, cce_block_width_p, lce_id_width_p, lce_assoc_p)
|
||||
|
||||
// , parameter [paddr_width_p-1:0] dram_offset_p = '0
|
||||
, localparam num_block_words_lp = cce_block_width_p / 64
|
||||
|
|
@ -25,84 +25,69 @@ module bp2wb_convertor
|
|||
, localparam wbone_addr_lbound = 3 //`BSG_SAFE_CLOG2(wbone_data_width / mem_granularity) //dword granularity
|
||||
, localparam total_datafetch_cycle_lp = cce_block_width_p / wbone_data_width
|
||||
, localparam total_datafetch_cycle_width = `BSG_SAFE_CLOG2(total_datafetch_cycle_lp)
|
||||
, localparam cached_addr_base = 32'h4000_4000// 32'h5000_0000
|
||||
, localparam cached_addr_base = 32'h7000_0000//6000_0000 //32'h4000_4000//
|
||||
)
|
||||
(input clk_i
|
||||
,(* mark_debug = "true" *) input reset_i
|
||||
( input clk_i
|
||||
,(* mark_debug = "true" *) input reset_i
|
||||
|
||||
// BP side
|
||||
,(* mark_debug = "true" *) input [cce_mem_msg_width_lp-1:0] mem_cmd_i
|
||||
,(* mark_debug = "true" *) input mem_cmd_v_i
|
||||
,(* mark_debug = "true" *) output mem_cmd_yumi_o
|
||||
// BP side
|
||||
,(* mark_debug = "true" *) input [cce_mem_msg_width_lp-1:0] mem_cmd_i
|
||||
,(* mark_debug = "true" *) input mem_cmd_v_i
|
||||
,(* mark_debug = "true" *) output mem_cmd_ready_o
|
||||
|
||||
, (* mark_debug = "true" *) output [cce_mem_msg_width_lp-1:0] mem_resp_o
|
||||
, output [cce_mem_msg_width_lp-1:0] mem_resp_o
|
||||
, (* mark_debug = "true" *) output mem_resp_v_o
|
||||
, (* mark_debug = "true" *) input mem_resp_ready_i
|
||||
, (* mark_debug = "true" *) input mem_resp_yumi_i
|
||||
|
||||
// Wishbone side
|
||||
, (* mark_debug = "true" *) input [63:0] dat_i
|
||||
, (* mark_debug = "true" *) output logic [63:0] dat_o
|
||||
, (* mark_debug = "true" *) input ack_i
|
||||
// , input err_i
|
||||
// , input rty_i
|
||||
, input err_i
|
||||
// , input rty_i
|
||||
, (* mark_debug = "true" *) output logic [wbone_addr_ubound-wbone_addr_lbound-1:0] adr_o//TODO: Double check!!!
|
||||
, (* mark_debug = "true" *) output logic stb_o
|
||||
, output cyc_o
|
||||
, output sel_o //TODO: double check!!!
|
||||
, output [7:0] sel_o //TODO: double check!!!
|
||||
, (* mark_debug = "true" *) output we_o
|
||||
, output [2:0] cti_o //TODO: hardwire in Litex
|
||||
, output [1:0] bte_o //TODO: hardwire in Litex
|
||||
|
||||
);
|
||||
|
||||
`declare_bp_me_if(paddr_width_p, cce_block_width_p, num_lce_p, lce_assoc_p);
|
||||
`declare_bp_me_if(paddr_width_p, cce_block_width_p, lce_id_width_p, lce_assoc_p);
|
||||
|
||||
//locals
|
||||
(* mark_debug = "true" *) logic [total_datafetch_cycle_width:0] ack_ctr = 0;
|
||||
(* mark_debug = "true" *) bp_cce_mem_msg_s mem_cmd_cast_i, mem_resp_cast_o, mem_cmd_r;
|
||||
(* mark_debug = "true" *) bp_cce_mem_msg_s mem_cmd_cast_i, mem_resp_cast_o, mem_cmd_debug;//, mem_cmd_debug2
|
||||
(* mark_debug = "true" *) logic ready_li, v_li, stb_justgotack;
|
||||
(* mark_debug = "true" *) logic [cce_block_width_p-1:0] data_lo;
|
||||
(* mark_debug = "true" *) logic [cce_block_width_p-1:0] data_li;
|
||||
(* mark_debug = "true" *) wire [paddr_width_p-1:0] mem_cmd_addr_l;
|
||||
(* mark_debug = "true" *) logic [paddr_width_p-1:0] addr_lo;
|
||||
(* mark_debug = "true" *) logic set_stb;
|
||||
(* mark_debug = "true" *) wire [63:0] data_little_end;
|
||||
|
||||
|
||||
//reset
|
||||
//TODO: reset ack_ctr here
|
||||
//Handshaking between Wishbone and BlackParrot through convertor
|
||||
//3.1.3:At every rising edge of [CLK_I] the terminating signal(ACK) is sampled. If it
|
||||
//is asserted, then [STB_O] is negated.
|
||||
|
||||
assign ready_li = ( ack_ctr == 0 );
|
||||
assign mem_cmd_yumi_o = mem_cmd_v_i && ready_li;//!stb_o then ready to take!
|
||||
|
||||
assign ready_li = ( ack_ctr == 0 ) & !set_stb & !mem_resp_v_o;
|
||||
assign mem_cmd_ready_o = ready_li;//!stb_o then ready to take!
|
||||
// assign v_li = (ack_ctr == total_datafetch_cycle_lp-1);
|
||||
assign mem_resp_v_o = mem_resp_ready_i & v_li;
|
||||
assign stb_o = (set_stb) && !stb_justgotack; //addresi mem_cmd_rdan aldigimiz icin 1 cycle geriden geliyo
|
||||
assign mem_resp_v_o = v_li;
|
||||
assign stb_o = (set_stb) && !stb_justgotack;
|
||||
assign cyc_o = stb_o;
|
||||
assign sel_o = 0;
|
||||
assign sel_o = 8'b11111111;
|
||||
assign cti_o = 0;
|
||||
assign bte_o = 0;
|
||||
|
||||
initial begin
|
||||
ack_ctr = 0;
|
||||
//stb_reset_lo =0;
|
||||
end
|
||||
|
||||
/* always_ff @(posedge clk_i)
|
||||
if ( mem_cmd_yumi_o )// || (ack_ctr > 0))
|
||||
begin
|
||||
data_li <= 0;
|
||||
set_stb <= 1;
|
||||
end
|
||||
*/
|
||||
|
||||
|
||||
//Flip stb after each ack--->RULE 3.20:
|
||||
|
||||
// Every time we get an ACK from WB, increment counter until the counter reaches to total_datafetch_cycle_lp
|
||||
assign data_little_end = dat_i;
|
||||
always_ff @(posedge clk_i)
|
||||
begin
|
||||
|
||||
|
|
@ -112,10 +97,17 @@ assign data_little_end = dat_i;
|
|||
set_stb <= 0;
|
||||
v_li <=0;
|
||||
end
|
||||
|
||||
else if (mem_cmd_yumi_o)
|
||||
else if (v_li)
|
||||
begin
|
||||
data_li <= 0;
|
||||
if (mem_resp_yumi_i)
|
||||
begin
|
||||
v_li <= 0;
|
||||
ack_ctr <= 0;
|
||||
end
|
||||
end
|
||||
else if (mem_cmd_v_i)
|
||||
begin
|
||||
//data_li <= 0;
|
||||
set_stb <= 1;
|
||||
v_li <= 0;
|
||||
stb_justgotack <= 0;
|
||||
|
|
@ -126,10 +118,9 @@ assign data_little_end = dat_i;
|
|||
if (ack_i)//stb should be negated after ack
|
||||
begin
|
||||
stb_justgotack <= 1;
|
||||
data_li[(ack_ctr*wbone_data_width) +: wbone_data_width] <= data_little_end;
|
||||
if ((ack_ctr == total_datafetch_cycle_lp-1) || (mem_cmd_addr_l < cached_addr_base && mem_cmd_r.msg_type == e_cce_mem_uc_wr )) //if uncached store, just one cycle is fine
|
||||
begin
|
||||
ack_ctr <= 0;
|
||||
data_li[(ack_ctr*wbone_data_width) +: wbone_data_width] <= dat_i;
|
||||
if ((ack_ctr == total_datafetch_cycle_lp-1) || (mem_cmd_addr_l < cached_addr_base && mem_cmd_r.header.msg_type == e_cce_mem_uc_wr )) //if uncached store, just one cycle is fine
|
||||
begin
|
||||
v_li <=1;
|
||||
set_stb <= 0;
|
||||
end
|
||||
|
|
@ -145,25 +136,23 @@ assign data_little_end = dat_i;
|
|||
end
|
||||
|
||||
//Packet Pass from BP to BP2WB
|
||||
assign mem_cmd_cast_i = mem_cmd_i;
|
||||
|
||||
bsg_dff_reset_en
|
||||
assign mem_cmd_cast_i = mem_cmd_i;
|
||||
bp_cce_mem_msg_s mem_cmd_r;
|
||||
bsg_dff_reset_en
|
||||
#(.width_p(cce_mem_msg_width_lp))
|
||||
mshr_reg
|
||||
(.clk_i(clk_i)
|
||||
,.reset_i(reset_i)
|
||||
,.en_i(mem_cmd_yumi_o)//when
|
||||
,.en_i(mem_cmd_v_i)//when
|
||||
,.data_i(mem_cmd_i)
|
||||
,.data_o(mem_cmd_r)
|
||||
);
|
||||
|
||||
|
||||
//Addr && Data && Command Pass from BP2WB to WB
|
||||
logic [wbone_addr_lbound-1:0] throw_away;
|
||||
assign mem_cmd_addr_l = mem_cmd_r.addr;
|
||||
assign mem_cmd_addr_l = mem_cmd_r.header.addr;
|
||||
assign data_lo = mem_cmd_r.data;
|
||||
logic [39:0] mem_cmd_addr_l_zero64;
|
||||
logic [7:0] partial;
|
||||
always_comb begin
|
||||
if( mem_cmd_addr_l < cached_addr_base )
|
||||
begin
|
||||
|
|
@ -174,41 +163,105 @@ assign data_little_end = dat_i;
|
|||
else
|
||||
begin
|
||||
mem_cmd_addr_l_zero64 = mem_cmd_addr_l >> 6 << 6;
|
||||
// addr_lo =
|
||||
{adr_o,throw_away} = mem_cmd_addr_l_zero64 + (ack_ctr*8);//TODO:careful
|
||||
// adr_o = addr_lo[wbone_addr_ubound-1:wbone_addr_lbound];
|
||||
dat_o = data_lo[(ack_ctr*wbone_data_width) +: wbone_data_width];
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
assign we_o = (mem_cmd_r.msg_type inside {e_cce_mem_uc_wr, e_cce_mem_wb});
|
||||
|
||||
//DEBUG
|
||||
|
||||
wire [3:0] typean;
|
||||
assign typean = mem_cmd_r.msg_type;
|
||||
wire [2:0] debug1;
|
||||
assign debug1 = (mem_cmd_r.addr[5:0]>>3);
|
||||
assign we_o = (mem_cmd_r.header.msg_type inside {e_cce_mem_uc_wr, e_cce_mem_wb});
|
||||
|
||||
//Data Pass from BP2WB to BP
|
||||
|
||||
wire [cce_block_width_p-1:0] rd_word_offset = mem_cmd_r.addr[3+:3];
|
||||
wire [cce_block_width_p-1:0] rd_word_offset = mem_cmd_r.header.addr[3+:3];
|
||||
//wire [cce_block_width_p-1:0] rd_byte_offset = mem_cmd_r.addr[0+:3];
|
||||
wire [cce_block_width_p-1:0] rd_bit_shift = rd_word_offset*64; // We rely on receiver to adjust bits
|
||||
|
||||
wire [cce_block_width_p-1:0] data_li_resp = (mem_cmd_r.msg_type == e_cce_mem_uc_rd)
|
||||
(* mark_debug = "true" *) wire [cce_block_width_p-1:0] data_li_resp = (mem_cmd_r.header.msg_type == e_cce_mem_uc_rd)
|
||||
? data_li >> rd_bit_shift
|
||||
: data_li;
|
||||
|
||||
|
||||
|
||||
assign mem_resp_cast_o = '{data : data_li_resp
|
||||
,payload : mem_cmd_r.payload
|
||||
,size : mem_cmd_r.size
|
||||
,addr : mem_cmd_r.addr
|
||||
,msg_type: mem_cmd_r.msg_type
|
||||
,header :'{payload : mem_cmd_r.header.payload
|
||||
,size : mem_cmd_r.header.size
|
||||
,addr : mem_cmd_r.header.addr
|
||||
,msg_type: mem_cmd_r.header.msg_type
|
||||
}
|
||||
};
|
||||
|
||||
assign mem_resp_o = mem_resp_cast_o;
|
||||
|
||||
/*********************************************/
|
||||
/*DEBUG SECTION*/
|
||||
|
||||
/* always_comb
|
||||
begin
|
||||
if (mem_cmd_yumi_o == 1)// && mem_cmd_addr_l >=32'h8000_0000)
|
||||
begin
|
||||
mem_cmd_debug = mem_cmd_i;
|
||||
if(mem_cmd_debug.addr >= 32'h80000000)
|
||||
begin
|
||||
$display("myarray == %x", mem_cmd_debug.addr);
|
||||
$display("myarray == %x", mem_cmd_debug.msg_type);
|
||||
if(mem_cmd_debug.msg_type>=3)
|
||||
$display("myarray == %x", mem_cmd_debug.data);
|
||||
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always_comb
|
||||
begin
|
||||
if(mem_resp_v_o)
|
||||
begin
|
||||
mem_cmd_debug2 = mem_resp_o;
|
||||
if(mem_cmd_debug2.addr >= 32'h80000000)
|
||||
begin
|
||||
$display("myresp == %x", mem_cmd_debug2.addr);
|
||||
$display("myresp == %x", mem_cmd_debug2.msg_type);
|
||||
if(mem_cmd_debug2.msg_type<=1)
|
||||
$display("myresp == %x", mem_cmd_debug2.data);
|
||||
end
|
||||
end
|
||||
end
|
||||
*/
|
||||
|
||||
/*wire [3:0] fake_msg_type;
|
||||
wire [10:0] fake_payload;
|
||||
wire [2:0] fake_size;
|
||||
wire [39:0] fake_addr;
|
||||
assign fake_payload = mem_cmd_r.header.payload;
|
||||
assign fake_size = mem_cmd_r.header.size;
|
||||
assign fake_addr = mem_cmd_r.header.addr;
|
||||
assign fake_msg_type = mem_cmd_r.header.msg_type;
|
||||
*/
|
||||
(* mark_debug = "true" *) logic debug_wire;
|
||||
initial begin
|
||||
debug_wire = 0;
|
||||
end
|
||||
|
||||
assign mem_cmd_debug = mem_cmd_i;
|
||||
|
||||
always_ff @(posedge clk_i)
|
||||
debug_wire <= (ack_i && mem_cmd_debug.header.addr >= 32'h80000000);
|
||||
|
||||
/* always_ff @(posedge clk_i)
|
||||
begin
|
||||
if(mem_cmd_v_i && mem_cmd_debug.header.addr >= 32'h80000000)
|
||||
begin
|
||||
debug_wire <= 1;
|
||||
// $display("addr == %x", mem_cmd_debug.header.addr);
|
||||
end*/
|
||||
/* if (mem_resp_v_o && debug_ctr < 64 && mem_cmd_debug.header.addr >= 32'h80000000)
|
||||
begin
|
||||
debug_gotdata[((debug_ctr-1)*512) +: 512] <= data_li_resp;
|
||||
$display("data == %x", data_li_resp);
|
||||
end*/
|
||||
// end
|
||||
|
||||
wire [3:0] typean;
|
||||
assign typean = mem_cmd_r.header.msg_type;
|
||||
|
||||
endmodule
|
||||
|
||||
|
|
|
|||
|
|
@ -77,7 +77,7 @@ class BlackParrotRV64(CPU):
|
|||
self.platform = platform
|
||||
self.variant = variant
|
||||
self.reset = Signal()
|
||||
self.interrupt = Signal(4)
|
||||
# self.interrupt = Signal(4)
|
||||
self.idbus = idbus = wishbone.Interface(data_width=64, adr_width=37)
|
||||
self.periph_buses = [idbus]
|
||||
self.memory_buses = []
|
||||
|
|
@ -118,8 +118,13 @@ class BlackParrotRV64(CPU):
|
|||
|
||||
@staticmethod
|
||||
def add_sources(platform, variant="standard"):
|
||||
filename = get_data_mod("cpu", "blackparrot").data_file(
|
||||
"flist_litex.verilator")
|
||||
simulation = 0
|
||||
if (simulation == 1):
|
||||
filename = get_data_mod("cpu", "blackparrot").data_file(
|
||||
"flist.verilator")
|
||||
else:
|
||||
filename = get_data_mod("cpu", "blackparrot").data_file(
|
||||
"flist.fpga")
|
||||
with open(filename) as openfileobject:
|
||||
for line in openfileobject:
|
||||
temp = line
|
||||
|
|
|
|||
|
|
@ -68,7 +68,7 @@ bss_loop:
|
|||
bss_done:
|
||||
|
||||
// call plic_init // initialize external interrupt controller
|
||||
# li a0, 0x800 // external interrupt sources only (using LiteX timer);
|
||||
li a0, 0x800 // external interrupt sources only (using LiteX timer);
|
||||
// NOTE: must still enable mstatus.MIE!
|
||||
csrw mie,a0
|
||||
|
||||
|
|
|
|||
|
|
@ -78,6 +78,8 @@ void isr(void)
|
|||
|
||||
#else
|
||||
|
||||
void isr(void){};
|
||||
void isr(void){
|
||||
printf("ISR blackparrot\n");
|
||||
};
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -1005,7 +1005,7 @@ int memtest(void)
|
|||
return 0;
|
||||
else {
|
||||
printf("Memtest OK\n");
|
||||
//memspeed();
|
||||
memspeed();
|
||||
return 1;
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -177,7 +177,7 @@ class SimSoC(SoCSDRAM):
|
|||
ident = "LiteX Simulation", ident_version=True,
|
||||
l2_reverse = False,
|
||||
**kwargs)
|
||||
self.add_constant("UART_POLLING",None)
|
||||
# self.add_constant("UART_POLLING",None)
|
||||
# CRG --------------------------------------------------------------------------------------
|
||||
self.submodules.crg = CRG(platform.request("sys_clk"))
|
||||
|
||||
|
|
@ -353,7 +353,7 @@ def main():
|
|||
with_analyzer = args.with_analyzer,
|
||||
sdram_init = [] if args.sdram_init is None else get_mem_data(args.sdram_init, cpu_endianness),
|
||||
**soc_kwargs)
|
||||
if args.ram_init is not None:
|
||||
if args.sdram_init is not None: #sdram_init
|
||||
soc.add_constant("ROM_BOOT_ADDRESS", 0x80000000)
|
||||
if args.with_ethernet:
|
||||
for i in range(4):
|
||||
|
|
|
|||
Loading…
Reference in a new issue