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cores/Video: Expose fifo_depth and add underflow signal that can be used investigate bandwidth issues.

This commit is contained in:
Florent Kermarrec 2021-03-29 10:58:31 +02:00
parent 544c0e2c84
commit bf999cfeac
1 changed files with 8 additions and 4 deletions
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12
litex/soc/cores/video.py
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@ -573,15 +573,16 @@ class VideoTerminal(Module):
class VideoFrameBuffer(Module, AutoCSR): class VideoFrameBuffer(Module, AutoCSR):
"""Video FrameBuffer""" """Video FrameBuffer"""
def __init__(self, dram_port, hres=800, vres=600, base=0x00000000, clock_domain="sys"): def __init__(self, dram_port, hres=800, vres=600, base=0x00000000, fifo_depth=8192, clock_domain="sys"):
self.vtg_sink = vtg_sink = stream.Endpoint(video_timing_layout) self.vtg_sink = vtg_sink = stream.Endpoint(video_timing_layout)
self.source = source = stream.Endpoint(video_data_layout) self.source = source = stream.Endpoint(video_data_layout)
self.underflow = Signal()
# # # # # #
# Video DMA. # Video DMA.
from litedram.frontend.dma import LiteDRAMDMAReader from litedram.frontend.dma import LiteDRAMDMAReader
self.submodules.dma = LiteDRAMDMAReader(dram_port, fifo_depth=2048, fifo_buffered=True) # FIXME: Adjust/Expose. self.submodules.dma = LiteDRAMDMAReader(dram_port, fifo_depth=fifo_depth//(dram_port.data_width//8), fifo_buffered=True)
self.dma.add_csr( self.dma.add_csr(
default_base = base, default_base = base,
default_length = hres*vres*32//8, # 32-bit RGB-444 default_length = hres*vres*32//8, # 32-bit RGB-444
@ -613,6 +614,9 @@ class VideoFrameBuffer(Module, AutoCSR):
source.b.eq(self.cdc.source.data[ 0: 8]), source.b.eq(self.cdc.source.data[ 0: 8]),
] ]
# Underflow.
self.comb += self.underflow.eq(~source.valid)
# Video PHYs --------------------------------------------------------------------------------------- # Video PHYs ---------------------------------------------------------------------------------------
class Open(Signal): pass class Open(Signal): pass