Hardware
/
litex
mirror of https://github.com/enjoy-digital/litex.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

platforms/versa_ecp5: add spiflash pads

This commit is contained in:
Florent Kermarrec 2019-07-22 10:25:55 +02:00
parent 41eb21b343
commit bfdcf4b2a0
1 changed files with 15 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

15
litex/boards/platforms/versa_ecp5.py
View File

@ -35,6 +35,21 @@ _io = [
Subsignal("tx", Pins("A11"), IOStandard("LVCMOS33")), Subsignal("tx", Pins("A11"), IOStandard("LVCMOS33")),
), ),
("spiflash", 0, # clock needs to be accessed through USRMCLK
Subsignal("cs_n", Pins("R2")),
Subsignal("mosi", Pins("W2")),
Subsignal("miso", Pins("V2")),
Subsignal("wp", Pins("Y2")),
Subsignal("hold", Pins("W1")),
IOStandard("LVCMOS33"),
),
("spiflash4x", 0, # clock needs to be accessed through USRMCLK
Subsignal("cs_n", Pins("R2")),
Subsignal("dq", Pins("W2 V2 Y2 W1")),
IOStandard("LVCMOS33")
),
("ddram", 0, ("ddram", 0,
Subsignal("a", Pins( Subsignal("a", Pins(
"P2 C4 E5 F5 B3 F4 B5 E4", "P2 C4 E5 F5 B3 F4 B5 E4",