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cpu/microwatt: simplify add_sources

This commit is contained in:
Florent Kermarrec 2019-12-17 09:41:46 +01:00
parent b9edde20de
commit bfe0bf6402
1 changed files with 34 additions and 32 deletions
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66
litex/soc/cores/cpu/microwatt/core.py
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@ -95,38 +95,40 @@ class Microwatt(CPU):
@staticmethod @staticmethod
def add_sources(platform): def add_sources(platform):
sdir = os.path.join(os.path.abspath(os.path.dirname(__file__)), "sources") sdir = os.path.join(os.path.abspath(os.path.dirname(__file__)), "sources")
platform.add_source(os.path.join(sdir, "decode_types.vhdl")) platform.add_source(sdir,
platform.add_source(os.path.join(sdir, "wishbone_types.vhdl")) "decode_types.vhdl",
platform.add_source(os.path.join(sdir, "common.vhdl")) "wishbone_types.vhdl",
platform.add_source(os.path.join(sdir, "fetch1.vhdl")) "common.vhdl",
platform.add_source(os.path.join(sdir, "fetch2.vhdl")) "fetch1.vhdl",
platform.add_source(os.path.join(sdir, "decode1.vhdl")) "fetch2.vhdl",
platform.add_source(os.path.join(sdir, "helpers.vhdl")) "decode1.vhdl",
platform.add_source(os.path.join(sdir, "decode2.vhdl")) "helpers.vhdl",
platform.add_source(os.path.join(sdir, "register_file.vhdl")) "decode2.vhdl",
platform.add_source(os.path.join(sdir, "cr_file.vhdl")) "register_file.vhdl",
platform.add_source(os.path.join(sdir, "crhelpers.vhdl")) "cr_file.vhdl",
platform.add_source(os.path.join(sdir, "ppc_fx_insns.vhdl")) "crhelpers.vhdl",
platform.add_source(os.path.join(sdir, "sim_console.vhdl")) "ppc_fx_insns.vhdl",
platform.add_source(os.path.join(sdir, "logical.vhdl")) "sim_console.vhdl",
platform.add_source(os.path.join(sdir, "countzero.vhdl")) "logical.vhdl",
platform.add_source(os.path.join(sdir, "gpr_hazard.vhdl")) "countzero.vhdl",
platform.add_source(os.path.join(sdir, "cr_hazard.vhdl")) "gpr_hazard.vhdl",
platform.add_source(os.path.join(sdir, "control.vhdl")) "cr_hazard.vhdl",
platform.add_source(os.path.join(sdir, "execute1.vhdl")) "control.vhdl",
platform.add_source(os.path.join(sdir, "loadstore1.vhdl")) "execute1.vhdl",
platform.add_source(os.path.join(sdir, "dcache.vhdl")) "loadstore1.vhdl",
platform.add_source(os.path.join(sdir, "multiply.vhdl")) "dcache.vhdl",
platform.add_source(os.path.join(sdir, "divider.vhdl")) "multiply.vhdl",
platform.add_source(os.path.join(sdir, "rotator.vhdl")) "divider.vhdl",
platform.add_source(os.path.join(sdir, "writeback.vhdl")) "rotator.vhdl",
platform.add_source(os.path.join(sdir, "insn_helpers.vhdl")) "writeback.vhdl",
platform.add_source(os.path.join(sdir, "core.vhdl")) "insn_helpers.vhdl",
platform.add_source(os.path.join(sdir, "icache.vhdl")) "core.vhdl",
platform.add_source(os.path.join(sdir, "plru.vhdl")) "icache.vhdl",
platform.add_source(os.path.join(sdir, "cache_ram.vhdl")) "plru.vhdl",
platform.add_source(os.path.join(sdir, "core_debug.vhdl")) "cache_ram.vhdl",
platform.add_source(os.path.join(sdir, "utils.vhdl")) "core_debug.vhdl",
"utils.vhdl"
)
platform.add_source(os.path.join(sdir, "..", "microwatt_wrapper.vhdl")) platform.add_source(os.path.join(sdir, "..", "microwatt_wrapper.vhdl"))
def do_finalize(self): def do_finalize(self):