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Merge pull request #214 from gsomlo/gls-alignment-fixup
soc_core: additional csr_alignment follow-up fixes
This commit is contained in:
commit
bff081a818
3 changed files with 7 additions and 3 deletions
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@ -186,11 +186,14 @@ class SoCCore(Module):
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# Parameters managment ---------------------------------------------------------------------
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# Parameters managment ---------------------------------------------------------------------
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# FIXME: RocketChip reserves the first 256Mbytes for internal use, change default mem_map
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# NOTE: RocketChip reserves the first 256Mbytes for internal use,
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# so we must change default mem_map;
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# Also, CSRs *must* be 64-bit aligned.
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if cpu_type == "rocket":
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if cpu_type == "rocket":
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self.soc_mem_map["rom"] = 0x10000000
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self.soc_mem_map["rom"] = 0x10000000
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self.soc_mem_map["sram"] = 0x11000000
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self.soc_mem_map["sram"] = 0x11000000
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self.soc_mem_map["csr"] = 0x12000000
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self.soc_mem_map["csr"] = 0x12000000
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csr_alignment = 64
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if cpu_type == "None":
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if cpu_type == "None":
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cpu_type = None
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cpu_type = None
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@ -536,7 +536,7 @@ static void read_level(int module)
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/* Write test pattern */
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/* Write test pattern */
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for(p=0;p<DFII_NPHASES;p++)
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for(p=0;p<DFII_NPHASES;p++)
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for(i=0;i<DFII_PIX_DATA_SIZE;i++)
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for(i=0;i<DFII_PIX_DATA_SIZE;i++)
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MMPTR(sdram_dfii_pix_wrdata_addr[p]+4*i) = prs[DFII_PIX_DATA_SIZE*p+i];
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MMPTR(sdram_dfii_pix_wrdata_addr[p]+DFII_ADDR_SHIFT*i) = prs[DFII_PIX_DATA_SIZE*p+i];
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sdram_dfii_piwr_address_write(0);
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sdram_dfii_piwr_address_write(0);
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sdram_dfii_piwr_baddress_write(0);
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sdram_dfii_piwr_baddress_write(0);
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command_pwr(DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS|DFII_COMMAND_WRDATA);
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command_pwr(DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS|DFII_COMMAND_WRDATA);
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@ -4,13 +4,14 @@
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#include <string.h>
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#include <string.h>
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#include <id.h>
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#include <id.h>
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#define DFII_ADDR_SHIFT CONFIG_CSR_ALIGNMENT/8
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void get_ident(char *ident)
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void get_ident(char *ident)
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{
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{
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#ifdef CSR_IDENTIFIER_MEM_BASE
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#ifdef CSR_IDENTIFIER_MEM_BASE
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int i;
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int i;
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for(i=0;i<256;i++)
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for(i=0;i<256;i++)
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ident[i] = MMPTR(CSR_IDENTIFIER_MEM_BASE + 4*i);
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ident[i] = MMPTR(CSR_IDENTIFIER_MEM_BASE + DFII_ADDR_SHIFT*i);
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#else
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#else
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ident[0] = 0;
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ident[0] = 0;
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#endif
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#endif
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