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build/xilinx/vivado: add vivado ip support

This commit is contained in:
Florent Kermarrec 2018-04-12 17:55:46 +02:00
parent 43f8c230a7
commit c001b8eaf6
2 changed files with 17 additions and 2 deletions
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4
litex/build/xilinx/platform.py
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@ -10,6 +10,7 @@ class XilinxPlatform(GenericPlatform):
def __init__(self, *args, toolchain="ise", **kwargs): def __init__(self, *args, toolchain="ise", **kwargs):
GenericPlatform.__init__(self, *args, **kwargs) GenericPlatform.__init__(self, *args, **kwargs)
self.edifs = set() self.edifs = set()
self.ips = set()
if toolchain == "ise": if toolchain == "ise":
self.toolchain = ise.XilinxISEToolchain() self.toolchain = ise.XilinxISEToolchain()
elif toolchain == "vivado": elif toolchain == "vivado":
@ -20,6 +21,9 @@ class XilinxPlatform(GenericPlatform):
def add_edif(self, filename): def add_edif(self, filename):
self.edifs.add((os.path.abspath(filename))) self.edifs.add((os.path.abspath(filename)))
def add_ip(self, filename):
self.ips.add((os.path.abspath(filename)))
def get_verilog(self, *args, special_overrides=dict(), **kwargs): def get_verilog(self, *args, special_overrides=dict(), **kwargs):
so = dict(common.xilinx_special_overrides) so = dict(common.xilinx_special_overrides)
if self.device[:3] == "xc6": if self.device[:3] == "xc6":

15
litex/build/xilinx/vivado.py
View File

@ -106,7 +106,7 @@ class XilinxVivadoToolchain:
self.clocks = dict() self.clocks = dict()
self.false_paths = set() self.false_paths = set()
def _build_batch(self, platform, sources, edifs, build_name): def _build_batch(self, platform, sources, edifs, ips, build_name):
tcl = [] tcl = []
tcl.append("create_project -force -name {} -part {}".format(build_name, platform.device)) tcl.append("create_project -force -name {} -part {}".format(build_name, platform.device))
for filename, language, library in sources: for filename, language, library in sources:
@ -117,6 +117,16 @@ class XilinxVivadoToolchain:
for filename in edifs: for filename in edifs:
filename_tcl = "{" + filename + "}" filename_tcl = "{" + filename + "}"
tcl.append("read_edif " + filename_tcl) tcl.append("read_edif " + filename_tcl)
for filename in ips:
filename_tcl = "{" + filename + "}"
ip = os.path.splitext(os.path.basename(filename))[0]
tcl.append("read_ip " + filename_tcl)
tcl.append("upgrade_ip [get_ips {}]".format(ip))
tcl.append("generate_target all [get_ips {}]".format(ip))
tcl.append("synth_ip [get_ips {}] -force".format(ip))
tcl.append("get_files -all -of_objects [get_files {}]".format(filename_tcl))
tcl.append("read_xdc {}.xdc".format(build_name)) tcl.append("read_xdc {}.xdc".format(build_name))
tcl.extend(c.format(build_name=build_name) for c in self.pre_synthesis_commands) tcl.extend(c.format(build_name=build_name) for c in self.pre_synthesis_commands)
# "-include_dirs {}" crashes Vivado 2016.4 # "-include_dirs {}" crashes Vivado 2016.4
@ -215,7 +225,8 @@ class XilinxVivadoToolchain:
v_output.write(v_file) v_output.write(v_file)
sources = platform.sources | {(v_file, "verilog", "work")} sources = platform.sources | {(v_file, "verilog", "work")}
edifs = platform.edifs edifs = platform.edifs
self._build_batch(platform, sources, edifs, build_name) ips = platform.ips
self._build_batch(platform, sources, edifs, ips, build_name)
tools.write_to_file(build_name + ".xdc", _build_xdc(named_sc, named_pc)) tools.write_to_file(build_name + ".xdc", _build_xdc(named_sc, named_pc))
if run: if run:
_run_vivado(build_name, toolchain_path, source) _run_vivado(build_name, toolchain_path, source)