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soc/cores: fix vivado issue with SPIRegister (at least with Vivado 2017.x+, mosi was not generated correctly), create cs_n signal if pads does not exists

This commit is contained in:
Florent Kermarrec 2017-07-27 18:22:01 +02:00
parent 04646b24ed
commit c02de1632b
1 changed files with 24 additions and 19 deletions
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27
litex/soc/cores/spi.py
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@ -45,18 +45,19 @@ class SPIRegister(Module):
self.o.eq(Mux(self.lsb, self.data[0], self.data[-1])), self.o.eq(Mux(self.lsb, self.data[0], self.data[-1])),
] ]
self.sync += [ self.sync += [
If(self.shift,
If(self.lsb, If(self.lsb,
self.data[:-1].eq(self.data[1:]), If(self.shift,
).Else( self.data[:-1].eq(self.data[1:])
self.data[1:].eq(self.data[:-1]),
)
), ),
If(self.sample, If(self.sample,
If(self.lsb, self.data[0].eq(self.i)
self.data[-1].eq(self.i), )
).Else( ).Else(
self.data[0].eq(self.i), If(self.shift,
self.data[1:].eq(self.data[:-1]),
),
If(self.sample,
self.data[0].eq(self.i)
) )
) )
] ]
@ -317,9 +318,12 @@ class SPIMasterCore(Module):
] ]
# I/O # I/O
if hasattr(pads, "cs_n"): if not hasattr(pads, "cs_n"):
cs_n_t = TSTriple(len(pads.cs_n)) self.cs_n = Signal()
self.specials += cs_n_t.get_tristate(pads.cs_n) else:
self.cs_n = pads.cs_n
cs_n_t = TSTriple(len(self.cs_n))
self.specials += cs_n_t.get_tristate(self.cs_n)
self.comb += [ self.comb += [
cs_n_t.oe.eq(~self.config.offline), cs_n_t.oe.eq(~self.config.offline),
cs_n_t.o.eq((cs & Replicate(machine.cs, len(cs))) ^ cs_n_t.o.eq((cs & Replicate(machine.cs, len(cs))) ^
@ -342,6 +346,7 @@ class SPIMasterCore(Module):
machine.reg.i.eq(Mux(self.config.half_duplex, mosi_t.i, machine.reg.i.eq(Mux(self.config.half_duplex, mosi_t.i,
getattr(pads, "miso", mosi_t.i))), getattr(pads, "miso", mosi_t.i))),
] ]
self.mosi_t = mosi_t
class SPIMaster(Module, AutoCSR): class SPIMaster(Module, AutoCSR):