Hardware
/
litex
mirror of https://github.com/enjoy-digital/litex.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

soc/cores: fix vivado issue with SPIRegister (at least with Vivado 2017.x+, mosi was not generated correctly), create cs_n signal if pads does not exists

This commit is contained in:
Florent Kermarrec 2017-07-27 18:22:01 +02:00
parent 04646b24ed
commit c02de1632b
1 changed files with 24 additions and 19 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

27
litex/soc/cores/spi.py
View File

@ -45,18 +45,19 @@ class SPIRegister(Module):
self.o.eq(Mux(self.lsb, self.data[0], self.data[-1])),
]
self.sync += [
If(self.shift,
If(self.lsb,
self.data[:-1].eq(self.data[1:]),
).Else(
self.data[1:].eq(self.data[:-1]),
)
If(self.shift,
self.data[:-1].eq(self.data[1:])
),
If(self.sample,
If(self.lsb,
self.data[-1].eq(self.i),
self.data[0].eq(self.i)
)
).Else(
self.data[0].eq(self.i),
If(self.shift,
self.data[1:].eq(self.data[:-1]),
),
If(self.sample,
self.data[0].eq(self.i)
)
)
]
@ -317,9 +318,12 @@ class SPIMasterCore(Module):
]
# I/O
if hasattr(pads, "cs_n"):
cs_n_t = TSTriple(len(pads.cs_n))
self.specials += cs_n_t.get_tristate(pads.cs_n)
if not hasattr(pads, "cs_n"):
self.cs_n = Signal()
else:
self.cs_n = pads.cs_n
cs_n_t = TSTriple(len(self.cs_n))
self.specials += cs_n_t.get_tristate(self.cs_n)
self.comb += [
cs_n_t.oe.eq(~self.config.offline),
cs_n_t.o.eq((cs & Replicate(machine.cs, len(cs))) ^
@ -342,6 +346,7 @@ class SPIMasterCore(Module):
machine.reg.i.eq(Mux(self.config.half_duplex, mosi_t.i,
getattr(pads, "miso", mosi_t.i))),
]
self.mosi_t = mosi_t
class SPIMaster(Module, AutoCSR):