boards: add new digilent arty
This commit is contained in:
Florent Kermarrec
parent
c24727ab4c
commit
c0539fff3e
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# This file is Copyright (c) 2015 Yann Sionneau <yann@sionneau.net>
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# This file is Copyright (c) 2015 Florent Kermarrec <florent@enjoy-digital.fr>
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# License: BSD
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from litex.build.generic_platform import *
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from litex.build.xilinx import XilinxPlatform, XC3SProg, VivadoProgrammer
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_io = [
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("user_led", 0, Pins("H5"), IOStandard("LVCMOS33")),
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("user_led", 1, Pins("J5"), IOStandard("LVCMOS33")),
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("user_led", 2, Pins("T9"), IOStandard("LVCMOS33")),
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("user_led", 3, Pins("T10"), IOStandard("LVCMOS33")),
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("rgb_leds", 0,
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Subsignal("r", Pins("G6 G3 J3 K1")),
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Subsignal("g", Pins("F6 J4 J2 H6")),
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Subsignal("b", Pins("E1 G4 H4 K2")),
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IOStandard("LVCMOS33")
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),
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("user_sw", 0, Pins("A8"), IOStandard("LVCMOS33")),
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("user_sw", 1, Pins("C11"), IOStandard("LVCMOS33")),
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("user_sw", 2, Pins("C10"), IOStandard("LVCMOS33")),
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("user_sw", 3, Pins("A10"), IOStandard("LVCMOS33")),
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("user_btn", 0, Pins("D9"), IOStandard("LVCMOS33")),
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("user_btn", 1, Pins("C9"), IOStandard("LVCMOS33")),
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("user_btn", 2, Pins("B9"), IOStandard("LVCMOS33")),
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("user_btn", 3, Pins("B8"), IOStandard("LVCMOS33")),
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("clk100", 0, Pins("E3"), IOStandard("LVCMOS33")),
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("cpu_reset", 0, Pins("C2"), IOStandard("LVCMOS33")),
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("serial", 0,
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Subsignal("tx", Pins("D10")),
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Subsignal("rx", Pins("A9")),
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IOStandard("LVCMOS33")),
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("spiflash", 0, # clock needs to be accessed through STARTUPE2
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Subsignal("cs_n", Pins("L13")),
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Subsignal("dq", Pins("K17", "K18", "L14", "M14")),
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IOStandard("LVCMOS33")
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),
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("eth_ref_clk", 0, Pins("G18"), IOStandard("LVCMOS33")),
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("ddram", 0,
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Subsignal("a", Pins(
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"R2 M6 N4 T1 N6 R7 V6 U7"),
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IOStandard("SSTL135")),
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Subsignal("ba", Pins("R1 P4 P2"), IOStandard("SSTL135")),
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Subsignal("ras_n", Pins("P3"), IOStandard("SSTL135")),
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Subsignal("cas_n", Pins("M4"), IOStandard("SSTL135")),
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Subsignal("we_n", Pins("P5"), IOStandard("SSTL135")),
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Subsignal("cs_n", Pins("U8"), IOStandard("SSTL135")),
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Subsignal("dm", Pins("L1"), IOStandard("SSTL135")),
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Subsignal("dq", Pins(
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"K5 L3 K3 L6 M3 M1 L4 M2"),
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IOStandard("SSTL135"),
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Misc("IN_TERM=UNTUNED_SPLIT_50")),
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Subsignal("dqs_p", Pins("N2"), IOStandard("DIFF_SSTL135")),
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Subsignal("dqs_n", Pins("N1"), IOStandard("DIFF_SSTL135")),
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Subsignal("clk_p", Pins("U9"), IOStandard("DIFF_SSTL135")),
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Subsignal("clk_n", Pins("V9"), IOStandard("DIFF_SSTL135")),
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Subsignal("cke", Pins("N5"), IOStandard("SSTL135")),
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Subsignal("odt", Pins("R5"), IOStandard("SSTL135")),
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Subsignal("reset_n", Pins("K6"), IOStandard("SSTL135")),
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Misc("SLEW=FAST"),
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),
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("eth_clocks", 0,
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Subsignal("tx", Pins("H16")),
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Subsignal("rx", Pins("F15")),
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IOStandard("LVCMOS33")
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),
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("eth", 0,
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Subsignal("rst_n", Pins("C16")),
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Subsignal("mdio", Pins("K13")),
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Subsignal("mdc", Pins("F16")),
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Subsignal("dv", Pins("G16")),
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Subsignal("rx_er", Pins("C17")),
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Subsignal("rx_data", Pins("D18 E17 E18 G17")),
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Subsignal("tx_en", Pins("H15")),
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Subsignal("tx_data", Pins("H14 J14 J13 H17")),
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Subsignal("col", Pins("D17")),
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Subsignal("crs", Pins("G14")),
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IOStandard("LVCMOS33")
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),
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]
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class Platform(XilinxPlatform):
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default_clk_name = "clk100"
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default_clk_period = 10.0
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def __init__(self, toolchain="vivado", programmer="vivado"):
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XilinxPlatform.__init__(self, "xc7a35ticsg324-1L", _io,
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toolchain=toolchain)
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self.toolchain.bitstream_commands = \
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["set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]"]
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self.toolchain.additional_commands = \
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["write_cfgmem -force -format bin -interface spix4 -size 16 "
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"-loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"]
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self.programmer = programmer
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self.add_platform_command("set_property INTERNAL_VREF 0.675 [get_iobanks 34]")
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def create_programmer(self):
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if self.programmer == "xc3sprog":
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return XC3SProg("nexys4")
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elif self.programmer == "vivado":
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return VivadoProgrammer(flash_part="n25q128-3.3v-spi-x1_x2_x4")
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else:
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raise ValueError("{} programmer is not supported"
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.format(self.programmer))
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@ -0,0 +1,132 @@
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#!/usr/bin/env python3
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import argparse
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import os
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from litex.gen import *
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from litex.gen.genlib.resetsync import AsyncResetSynchronizer
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from litex.boards.platforms import arty
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.builder import *
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from liteeth.phy.mii import LiteEthPHYMII
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from liteeth.core.mac import LiteEthMAC
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class _CRG(Module):
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def __init__(self, platform):
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_eth = ClockDomain(reset_less=True)
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clk100 = platform.request("clk100")
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rst = platform.request("cpu_reset")
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pll_locked = Signal()
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pll_fb = Signal()
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pll_sys = Signal()
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pll_eth = Signal()
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self.specials += [
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Instance("PLLE2_BASE",
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p_STARTUP_WAIT="FALSE", o_LOCKED=pll_locked,
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# VCO @ 800 MHz
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p_REF_JITTER1=0.01, p_CLKIN1_PERIOD=10.0,
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p_CLKFBOUT_MULT=8, p_DIVCLK_DIVIDE=1,
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i_CLKIN1=clk100, i_CLKFBIN=pll_fb, o_CLKFBOUT=pll_fb,
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# 100 MHz
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p_CLKOUT0_DIVIDE=8, p_CLKOUT0_PHASE=0.0,
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o_CLKOUT0=pll_sys,
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# 25 MHz
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p_CLKOUT1_DIVIDE=32, p_CLKOUT1_PHASE=0.0,
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o_CLKOUT1=pll_eth,
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# 200 MHz
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p_CLKOUT2_DIVIDE=4, p_CLKOUT2_PHASE=0.0,
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#o_CLKOUT2=,
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# 200 MHz
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p_CLKOUT3_DIVIDE=4, p_CLKOUT3_PHASE=0.0,
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#o_CLKOUT3=,
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# 200MHz
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p_CLKOUT4_DIVIDE=4, p_CLKOUT4_PHASE=0.0,
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#o_CLKOUT4=
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),
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Instance("BUFG", i_I=pll_sys, o_O=self.cd_sys.clk),
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Instance("BUFG", i_I=pll_eth, o_O=self.cd_eth.clk),
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AsyncResetSynchronizer(self.cd_sys, ~pll_locked | ~rst),
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]
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self.specials += [
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Instance("ODDR2", p_DDR_ALIGNMENT="NONE",
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p_INIT=0, p_SRTYPE="SYNC",
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i_D0=0, i_D1=1, i_S=0, i_R=0, i_CE=1,
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i_C0=self.cd_eth.clk, i_C1=~self.cd_eth.clk,
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o_Q=platform.request("eth_ref_clk"))
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]
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class BaseSoC(SoCCore):
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def __init__(self, **kwargs):
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platform = arty.Platform()
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SoCCore.__init__(self, platform, clk_freq=100*1000000, **kwargs)
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self.submodules.crg = _CRG(platform)
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class MiniSoC(BaseSoC):
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csr_map = {
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"ethphy": 18,
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"ethmac": 19
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}
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csr_map.update(BaseSoC.csr_map)
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interrupt_map = {
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"ethmac": 2,
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}
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interrupt_map.update(BaseSoC.interrupt_map)
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mem_map = {
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"ethmac": 0x30000000, # (shadow @0xb0000000)
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}
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mem_map.update(BaseSoC.mem_map)
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def __init__(self, **kwargs):
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BaseSoC.__init__(self, **kwargs)
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self.submodules.ethphy = LiteEthPHYMII(self.platform.request("eth_clocks"),
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self.platform.request("eth"))
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self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone")
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self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus)
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self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000)
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def main():
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parser = argparse.ArgumentParser(description="LiteX SoC port to Arty")
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builder_args(parser)
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soc_core_args(parser)
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parser.add_argument("--with-ethernet", action="store_true",
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help="enable Ethernet support")
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parser.add_argument("--build", action="store_true",
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help="build bitstream")
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parser.add_argument("--load", action="store_true",
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help="load bitstream")
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args = parser.parse_args()
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cls = MiniSoC if args.with_ethernet else BaseSoC
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soc = cls(**soc_core_argdict(args))
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builder = Builder(soc, **builder_argdict(args))
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if args.build:
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builder.build()
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if args.load:
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prog = soc.platform.create_programmer()
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prog.load_bitstream(os.path.join(builder.output_dir, "gateware", "top.bit"))
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if __name__ == "__main__":
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main()
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