boards/targets: remove papilio_pro/pipistrello
This commit is contained in:
Florent Kermarrec
parent
352cb91688
commit
c076c2cbd6
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@ -1,108 +0,0 @@
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#!/usr/bin/env python3
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import argparse
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from fractions import Fraction
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from migen import *
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from litex.boards.platforms import papilio_pro
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from litex.soc.cores.sdram.settings import MT48LC4M16
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from litex.soc.cores.sdram.phy import GENSDRPHY
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from litex.soc.cores.flash import spi_flash
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from litex.soc.integration.soc_sdram import *
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from litex.soc.integration.builder import *
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class _CRG(Module):
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def __init__(self, platform, clk_freq):
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_sys_ps = ClockDomain()
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f0 = 32*1000000
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clk32 = platform.request("clk32")
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clk32a = Signal()
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self.specials += Instance("IBUFG", i_I=clk32, o_O=clk32a)
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clk32b = Signal()
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self.specials += Instance("BUFIO2", p_DIVIDE=1,
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p_DIVIDE_BYPASS="TRUE", p_I_INVERT="FALSE",
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i_I=clk32a, o_DIVCLK=clk32b)
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f = Fraction(int(clk_freq), int(f0))
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n, m, p = f.denominator, f.numerator, 8
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assert f0/n*m == clk_freq
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pll_lckd = Signal()
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pll_fb = Signal()
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pll = Signal(6)
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self.specials.pll = Instance("PLL_ADV", p_SIM_DEVICE="SPARTAN6",
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p_BANDWIDTH="OPTIMIZED", p_COMPENSATION="INTERNAL",
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p_REF_JITTER=.01, p_CLK_FEEDBACK="CLKFBOUT",
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i_DADDR=0, i_DCLK=0, i_DEN=0, i_DI=0, i_DWE=0, i_RST=0, i_REL=0,
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p_DIVCLK_DIVIDE=1, p_CLKFBOUT_MULT=m*p//n, p_CLKFBOUT_PHASE=0.,
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i_CLKIN1=clk32b, i_CLKIN2=0, i_CLKINSEL=1,
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p_CLKIN1_PERIOD=1000000000/f0, p_CLKIN2_PERIOD=0.,
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i_CLKFBIN=pll_fb, o_CLKFBOUT=pll_fb, o_LOCKED=pll_lckd,
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o_CLKOUT0=pll[0], p_CLKOUT0_DUTY_CYCLE=.5,
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o_CLKOUT1=pll[1], p_CLKOUT1_DUTY_CYCLE=.5,
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o_CLKOUT2=pll[2], p_CLKOUT2_DUTY_CYCLE=.5,
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o_CLKOUT3=pll[3], p_CLKOUT3_DUTY_CYCLE=.5,
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o_CLKOUT4=pll[4], p_CLKOUT4_DUTY_CYCLE=.5,
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o_CLKOUT5=pll[5], p_CLKOUT5_DUTY_CYCLE=.5,
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p_CLKOUT0_PHASE=0., p_CLKOUT0_DIVIDE=p//1,
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p_CLKOUT1_PHASE=0., p_CLKOUT1_DIVIDE=p//1,
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p_CLKOUT2_PHASE=0., p_CLKOUT2_DIVIDE=p//1,
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p_CLKOUT3_PHASE=0., p_CLKOUT3_DIVIDE=p//1,
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p_CLKOUT4_PHASE=0., p_CLKOUT4_DIVIDE=p//1, # sys
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p_CLKOUT5_PHASE=270., p_CLKOUT5_DIVIDE=p//1, # sys_ps
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)
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self.specials += Instance("BUFG", i_I=pll[4], o_O=self.cd_sys.clk)
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self.specials += Instance("BUFG", i_I=pll[5], o_O=self.cd_sys_ps.clk)
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self.specials += AsyncResetSynchronizer(self.cd_sys, ~pll_lckd)
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self.specials += Instance("ODDR2", p_DDR_ALIGNMENT="NONE",
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p_INIT=0, p_SRTYPE="SYNC",
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i_D0=0, i_D1=1, i_S=0, i_R=0, i_CE=1,
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i_C0=self.cd_sys.clk, i_C1=~self.cd_sys.clk,
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o_Q=platform.request("sdram_clock"))
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class BaseSoC(SoCSDRAM):
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csr_map = {
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"spiflash": 16,
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}
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csr_map.update(SoCSDRAM.csr_map)
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def __init__(self, **kwargs):
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platform = papilio_pro.Platform()
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clk_freq = 80*1000000
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SoCSDRAM.__init__(self, platform, clk_freq,
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cpu_reset_address=0x60000,
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**kwargs)
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self.submodules.crg = _CRG(platform, clk_freq)
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if not self.integrated_main_ram_size:
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self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"))
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sdram_module = MT48LC4M16(clk_freq)
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self.register_sdram(self.sdrphy, "minicon",
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sdram_module.geom_settings, sdram_module.timing_settings)
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if not self.integrated_rom_size:
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self.submodules.spiflash = spi_flash.SpiFlash(platform.request("spiflash2x"),
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dummy=4, div=6)
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self.flash_boot_address = 0x70000
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self.register_rom(self.spiflash.bus)
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def main():
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parser = argparse.ArgumentParser(description="LiteX SoC port to the Papilio Pro")
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builder_args(parser)
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soc_sdram_args(parser)
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args = parser.parse_args()
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soc = BaseSoC(**soc_sdram_argdict(args))
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builder = Builder(soc, **builder_argdict(args))
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builder.build()
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if __name__ == "__main__":
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main()
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@ -1,151 +0,0 @@
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#!/usr/bin/env python3
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import argparse
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from fractions import Fraction
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from migen import *
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from litex.boards.platforms import pipistrello
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from litex.soc.cores.sdram_settings import MT46H32M16
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from litex.soc.cores.sdram_phy import S6HalfRateDDRPHY
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from litex.soc.cores.flash import spi_flash
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from litex.soc.integration.soc_sdram import *
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from litex.soc.integration.builder import *
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class _CRG(Module):
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def __init__(self, platform, clk_freq):
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_sdram_half = ClockDomain()
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self.clock_domains.cd_sdram_full_wr = ClockDomain()
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self.clock_domains.cd_sdram_full_rd = ClockDomain()
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self.clk4x_wr_strb = Signal()
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self.clk4x_rd_strb = Signal()
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f0 = Fraction(50, 1)*1000000
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p = 12
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f = Fraction(clk_freq*p, f0)
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n, d = f.numerator, f.denominator
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assert 19e6 <= f0/d <= 500e6 # pfd
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assert 400e6 <= f0*n/d <= 1080e6 # vco
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clk50 = platform.request("clk50")
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clk50a = Signal()
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self.specials += Instance("IBUFG", i_I=clk50, o_O=clk50a)
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clk50b = Signal()
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self.specials += Instance("BUFIO2", p_DIVIDE=1,
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p_DIVIDE_BYPASS="TRUE", p_I_INVERT="FALSE",
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i_I=clk50a, o_DIVCLK=clk50b)
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pll_lckd = Signal()
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pll_fb = Signal()
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pll = Signal(6)
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self.specials.pll = Instance("PLL_ADV", p_SIM_DEVICE="SPARTAN6",
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p_BANDWIDTH="OPTIMIZED", p_COMPENSATION="INTERNAL",
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p_REF_JITTER=.01, p_CLK_FEEDBACK="CLKFBOUT",
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i_DADDR=0, i_DCLK=0, i_DEN=0, i_DI=0, i_DWE=0, i_RST=0, i_REL=0,
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p_DIVCLK_DIVIDE=d, p_CLKFBOUT_MULT=n, p_CLKFBOUT_PHASE=0.,
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i_CLKIN1=clk50b, i_CLKIN2=0, i_CLKINSEL=1,
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p_CLKIN1_PERIOD=1e9/f0, p_CLKIN2_PERIOD=0.,
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i_CLKFBIN=pll_fb, o_CLKFBOUT=pll_fb, o_LOCKED=pll_lckd,
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o_CLKOUT0=pll[0], p_CLKOUT0_DUTY_CYCLE=.5,
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o_CLKOUT1=pll[1], p_CLKOUT1_DUTY_CYCLE=.5,
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o_CLKOUT2=pll[2], p_CLKOUT2_DUTY_CYCLE=.5,
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o_CLKOUT3=pll[3], p_CLKOUT3_DUTY_CYCLE=.5,
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o_CLKOUT4=pll[4], p_CLKOUT4_DUTY_CYCLE=.5,
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o_CLKOUT5=pll[5], p_CLKOUT5_DUTY_CYCLE=.5,
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p_CLKOUT0_PHASE=0., p_CLKOUT0_DIVIDE=p//4, # sdram wr rd
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p_CLKOUT1_PHASE=0., p_CLKOUT1_DIVIDE=p//4,
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p_CLKOUT2_PHASE=270., p_CLKOUT2_DIVIDE=p//2, # sdram dqs adr ctrl
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p_CLKOUT3_PHASE=250., p_CLKOUT3_DIVIDE=p//2, # off-chip ddr
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p_CLKOUT4_PHASE=0., p_CLKOUT4_DIVIDE=p//1,
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p_CLKOUT5_PHASE=0., p_CLKOUT5_DIVIDE=p//1, # sys
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)
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self.specials += Instance("BUFG", i_I=pll[5], o_O=self.cd_sys.clk)
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reset = platform.request("user_btn")
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self.clock_domains.cd_por = ClockDomain()
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por = Signal(max=1 << 11, reset=(1 << 11) - 1)
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self.sync.por += If(por != 0, por.eq(por - 1))
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self.comb += self.cd_por.clk.eq(self.cd_sys.clk)
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self.specials += AsyncResetSynchronizer(self.cd_por, reset)
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self.specials += AsyncResetSynchronizer(self.cd_sys, ~pll_lckd | (por > 0))
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self.specials += Instance("BUFG", i_I=pll[2], o_O=self.cd_sdram_half.clk)
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self.specials += Instance("BUFPLL", p_DIVIDE=4,
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i_PLLIN=pll[0], i_GCLK=self.cd_sys.clk,
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i_LOCKED=pll_lckd, o_IOCLK=self.cd_sdram_full_wr.clk,
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o_SERDESSTROBE=self.clk4x_wr_strb)
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self.comb += [
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self.cd_sdram_full_rd.clk.eq(self.cd_sdram_full_wr.clk),
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self.clk4x_rd_strb.eq(self.clk4x_wr_strb),
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]
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clk_sdram_half_shifted = Signal()
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self.specials += Instance("BUFG", i_I=pll[3], o_O=clk_sdram_half_shifted)
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clk = platform.request("ddram_clock")
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self.specials += Instance("ODDR2", p_DDR_ALIGNMENT="NONE",
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p_INIT=0, p_SRTYPE="SYNC",
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i_D0=1, i_D1=0, i_S=0, i_R=0, i_CE=1,
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i_C0=clk_sdram_half_shifted, i_C1=~clk_sdram_half_shifted,
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o_Q=clk.p)
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self.specials += Instance("ODDR2", p_DDR_ALIGNMENT="NONE",
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p_INIT=0, p_SRTYPE="SYNC",
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i_D0=0, i_D1=1, i_S=0, i_R=0, i_CE=1,
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i_C0=clk_sdram_half_shifted, i_C1=~clk_sdram_half_shifted,
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o_Q=clk.n)
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class BaseSoC(SoCSDRAM):
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csr_map = {
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"spiflash": 16,
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}
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csr_map.update(SoCSDRAM.csr_map)
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def __init__(self, clk_freq=(83 + Fraction(1, 3))*1000*1000, **kwargs):
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platform = pipistrello.Platform()
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SoCSDRAM.__init__(self, platform, clk_freq,
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cpu_reset_address=0x170000, # 1.5 MB
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**kwargs)
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self.submodules.crg = _CRG(platform, clk_freq)
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if not self.integrated_main_ram_size:
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sdram_module = MT46H32M16(self.clk_freq)
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self.submodules.ddrphy = S6HalfRateDDRPHY(platform.request("ddram"),
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sdram_module.memtype,
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rd_bitslip=1,
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wr_bitslip=3,
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dqs_ddr_alignment="C1")
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self.comb += [
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self.ddrphy.clk4x_wr_strb.eq(self.crg.clk4x_wr_strb),
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self.ddrphy.clk4x_rd_strb.eq(self.crg.clk4x_rd_strb),
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]
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self.register_sdram(self.ddrphy, "minicon",
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sdram_module.geom_settings, sdram_module.timing_settings)
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if not self.integrated_rom_size:
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self.submodules.spiflash = spi_flash.SpiFlash(platform.request("spiflash4x"),
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dummy=10, div=4)
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self.add_constant("SPIFLASH_PAGE_SIZE", 256)
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self.add_constant("SPIFLASH_SECTOR_SIZE", 0x10000)
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self.flash_boot_address = 0x180000
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self.register_rom(self.spiflash.bus, 0x1000000)
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soc_pipistrello_args = soc_sdram_args
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soc_pipistrello_argdict = soc_sdram_argdict
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def main():
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parser = argparse.ArgumentParser(description="LiteX SoC port to the Pipistrello")
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builder_args(parser)
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soc_pipistrello_args(parser)
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args = parser.parse_args()
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soc = BaseSoC(**soc_pipistrello_argdict(args))
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builder = Builder(soc, **builder_argdict(args))
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builder.build()
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if __name__ == "__main__":
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main()
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