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cores/clock: only use locked on AsyncResetSynchronizer (already falling on reset) and add delay to reset to prevent interlocks with BIOS reboot command on Xilinx devices.

This commit is contained in:
Florent Kermarrec 2020-11-05 19:43:11 +01:00
parent 3e47a6e48b
commit c088cd5d22
1 changed files with 11 additions and 4 deletions
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15
litex/soc/cores/clock.py
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@ -98,7 +98,7 @@ class XilinxClocking(Module, AutoCSR):
clkout = Signal() clkout = Signal()
self.clkouts[self.nclkouts] = (clkout, freq, phase, margin) self.clkouts[self.nclkouts] = (clkout, freq, phase, margin)
if with_reset: if with_reset:
self.specials += AsyncResetSynchronizer(cd, ~self.locked | self.reset) self.specials += AsyncResetSynchronizer(cd, ~self.locked)
if buf is None: if buf is None:
self.comb += cd.clk.eq(clkout) self.comb += cd.clk.eq(clkout)
else: else:
@ -193,8 +193,15 @@ class XilinxClocking(Module, AutoCSR):
self.comb += self.drp_locked.status.eq(self.locked) self.comb += self.drp_locked.status.eq(self.locked)
self.logger.info("Exposing DRP interface.") self.logger.info("Exposing DRP interface.")
def add_reset_delay(self, cycles):
for i in range(cycles):
reset = Signal()
self.specials += Instance("FD", i_C=self.clkin, i_D=self.reset, o_Q=reset)
self.reset = reset
def do_finalize(self): def do_finalize(self):
assert hasattr(self, "clkin") assert hasattr(self, "clkin")
self.add_reset_delay(cycles=8) # Prevents interlock when reset driven from sys_clk.
# Xilinx / Spartan6 -------------------------------------------------------------------------------- # Xilinx / Spartan6 --------------------------------------------------------------------------------
@ -679,7 +686,7 @@ class iCE40PLL(Module):
clkout = Signal() clkout = Signal()
self.clkouts[self.nclkouts] = (clkout, freq, 0, margin) self.clkouts[self.nclkouts] = (clkout, freq, 0, margin)
if with_reset: if with_reset:
self.specials += AsyncResetSynchronizer(cd, ~self.locked | self.reset) self.specials += AsyncResetSynchronizer(cd, ~self.locked)
self.comb += cd.clk.eq(clkout) self.comb += cd.clk.eq(clkout)
create_clkout_log(self.logger, cd.name, freq, margin, self.nclkouts) create_clkout_log(self.logger, cd.name, freq, margin, self.nclkouts)
self.nclkouts += 1 self.nclkouts += 1
@ -781,7 +788,7 @@ class ECP5PLL(Module):
clkout = Signal() clkout = Signal()
self.clkouts[self.nclkouts] = (clkout, freq, phase, margin) self.clkouts[self.nclkouts] = (clkout, freq, phase, margin)
if with_reset: if with_reset:
self.specials += AsyncResetSynchronizer(cd, ~self.locked | self.reset) self.specials += AsyncResetSynchronizer(cd, ~self.locked)
self.comb += cd.clk.eq(clkout) self.comb += cd.clk.eq(clkout)
create_clkout_log(self.logger, cd.name, freq, margin, self.nclkouts) create_clkout_log(self.logger, cd.name, freq, margin, self.nclkouts)
self.nclkouts += 1 self.nclkouts += 1
@ -958,7 +965,7 @@ class IntelClocking(Module, AutoCSR):
clkout = Signal() clkout = Signal()
self.clkouts[self.nclkouts] = (clkout, freq, phase, margin) self.clkouts[self.nclkouts] = (clkout, freq, phase, margin)
if with_reset: if with_reset:
self.specials += AsyncResetSynchronizer(cd, ~self.locked | self.reset) self.specials += AsyncResetSynchronizer(cd, ~self.locked)
self.comb += cd.clk.eq(clkout) self.comb += cd.clk.eq(clkout)
create_clkout_log(self.logger, cd.name, freq, margin, self.nclkouts) create_clkout_log(self.logger, cd.name, freq, margin, self.nclkouts)
self.nclkouts += 1 self.nclkouts += 1