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sdram/lasmicon: create a separate file for the crossbar and remove it from lasmibus
This commit is contained in:
Florent Kermarrec
parent
7300879b7f
commit
c0b38e4905
3 changed files with 178 additions and 171 deletions
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@ -33,176 +33,6 @@ class Interface(Record):
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]
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Record.__init__(self, layout)
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def _getattr_all(l, attr):
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it = iter(l)
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r = getattr(next(it), attr)
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for e in it:
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if getattr(e, attr) != r:
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raise ValueError
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return r
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class Crossbar(Module):
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def __init__(self, controllers, cba_shift):
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self._controllers = controllers
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self._cba_shift = cba_shift
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self._rca_bits = _getattr_all(controllers, "aw")
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self._dw = _getattr_all(controllers, "dw")
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self._nbanks = _getattr_all(controllers, "nbanks")
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self._req_queue_size = _getattr_all(controllers, "req_queue_size")
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self._read_latency = _getattr_all(controllers, "read_latency")
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self._write_latency = _getattr_all(controllers, "write_latency")
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self._bank_bits = log2_int(self._nbanks, False)
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self._controller_bits = log2_int(len(self._controllers), False)
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self._masters = []
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def get_master(self):
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if self.finalized:
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raise FinalizeError
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lasmi_master = Interface(self._rca_bits + self._bank_bits + self._controller_bits,
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self._dw, 1, self._req_queue_size, self._read_latency, self._write_latency)
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self._masters.append(lasmi_master)
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return lasmi_master
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def do_finalize(self):
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nmasters = len(self._masters)
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m_ca, m_ba, m_rca = self._split_master_addresses(self._controller_bits,
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self._bank_bits, self._rca_bits, self._cba_shift)
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for nc, controller in enumerate(self._controllers):
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if self._controller_bits:
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controller_selected = [ca == nc for ca in m_ca]
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else:
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controller_selected = [1]*nmasters
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master_req_acks = [0]*nmasters
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master_dat_w_acks = [0]*nmasters
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master_dat_r_acks = [0]*nmasters
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rrs = [roundrobin.RoundRobin(nmasters, roundrobin.SP_CE) for n in range(self._nbanks)]
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self.submodules += rrs
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for nb, rr in enumerate(rrs):
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bank = getattr(controller, "bank"+str(nb))
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# for each master, determine if another bank locks it
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master_locked = []
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for nm, master in enumerate(self._masters):
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locked = 0
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for other_nb, other_rr in enumerate(rrs):
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if other_nb != nb:
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other_bank = getattr(controller, "bank"+str(other_nb))
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locked = locked | (other_bank.lock & (other_rr.grant == nm))
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master_locked.append(locked)
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# arbitrate
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bank_selected = [cs & (ba == nb) & ~locked for cs, ba, locked in zip(controller_selected, m_ba, master_locked)]
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bank_requested = [bs & master.stb for bs, master in zip(bank_selected, self._masters)]
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self.comb += [
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rr.request.eq(Cat(*bank_requested)),
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rr.ce.eq(~bank.stb & ~bank.lock)
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]
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# route requests
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self.comb += [
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bank.adr.eq(Array(m_rca)[rr.grant]),
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bank.we.eq(Array(self._masters)[rr.grant].we),
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bank.stb.eq(Array(bank_requested)[rr.grant])
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]
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master_req_acks = [master_req_ack | ((rr.grant == nm) & bank_selected[nm] & bank.req_ack)
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for nm, master_req_ack in enumerate(master_req_acks)]
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master_dat_w_acks = [master_dat_w_ack | ((rr.grant == nm) & bank.dat_w_ack)
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for nm, master_dat_w_ack in enumerate(master_dat_w_acks)]
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master_dat_r_acks = [master_dat_r_ack | ((rr.grant == nm) & bank.dat_r_ack)
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for nm, master_dat_r_ack in enumerate(master_dat_r_acks)]
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for nm, master_dat_w_ack in enumerate(master_dat_w_acks):
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for i in range(self._write_latency):
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new_master_dat_w_ack = Signal()
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self.sync += new_master_dat_w_ack.eq(master_dat_w_ack)
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master_dat_w_ack = new_master_dat_w_ack
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master_dat_w_acks[nm] = master_dat_w_ack
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for nm, master_dat_r_ack in enumerate(master_dat_r_acks):
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for i in range(self._read_latency):
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new_master_dat_r_ack = Signal()
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self.sync += new_master_dat_r_ack.eq(master_dat_r_ack)
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master_dat_r_ack = new_master_dat_r_ack
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master_dat_r_acks[nm] = master_dat_r_ack
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self.comb += [master.req_ack.eq(master_req_ack) for master, master_req_ack in zip(self._masters, master_req_acks)]
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self.comb += [master.dat_w_ack.eq(master_dat_w_ack) for master, master_dat_w_ack in zip(self._masters, master_dat_w_acks)]
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self.comb += [master.dat_r_ack.eq(master_dat_r_ack) for master, master_dat_r_ack in zip(self._masters, master_dat_r_acks)]
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# route data writes
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controller_selected_wl = controller_selected
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for i in range(self._write_latency):
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n_controller_selected_wl = [Signal() for i in range(nmasters)]
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self.sync += [n.eq(o) for n, o in zip(n_controller_selected_wl, controller_selected_wl)]
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controller_selected_wl = n_controller_selected_wl
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dat_w_maskselect = []
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dat_we_maskselect = []
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for master, selected in zip(self._masters, controller_selected_wl):
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o_dat_w = Signal(self._dw)
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o_dat_we = Signal(self._dw//8)
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self.comb += If(selected,
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o_dat_w.eq(master.dat_w),
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o_dat_we.eq(master.dat_we)
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)
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dat_w_maskselect.append(o_dat_w)
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dat_we_maskselect.append(o_dat_we)
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self.comb += [
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controller.dat_w.eq(optree("|", dat_w_maskselect)),
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controller.dat_we.eq(optree("|", dat_we_maskselect))
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]
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# route data reads
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if self._controller_bits:
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for master in self._masters:
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controller_sel = Signal(self._controller_bits)
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for nc, controller in enumerate(self._controllers):
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for nb in range(nbanks):
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bank = getattr(controller, "bank"+str(nb))
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self.comb += If(bank.stb & bank.ack, controller_sel.eq(nc))
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for i in range(self._read_latency):
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n_controller_sel = Signal(self._controller_bits)
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self.sync += n_controller_sel.eq(controller_sel)
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controller_sel = n_controller_sel
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self.comb += master.dat_r.eq(Array(self._controllers)[controller_sel].dat_r)
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else:
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self.comb += [master.dat_r.eq(self._controllers[0].dat_r) for master in self._masters]
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def _split_master_addresses(self, controller_bits, bank_bits, rca_bits, cba_shift):
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m_ca = [] # controller address
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m_ba = [] # bank address
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m_rca = [] # row and column address
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for master in self._masters:
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cba = Signal(self._controller_bits + self._bank_bits)
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rca = Signal(self._rca_bits)
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cba_upper = cba_shift + controller_bits + bank_bits
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self.comb += cba.eq(master.adr[cba_shift:cba_upper])
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if cba_shift < self._rca_bits:
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if cba_shift:
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self.comb += rca.eq(Cat(master.adr[:cba_shift], master.adr[cba_upper:]))
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else:
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self.comb += rca.eq(master.adr[cba_upper:])
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else:
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self.comb += rca.eq(master.adr[:cba_shift])
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if self._controller_bits:
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ca = Signal(self._controller_bits)
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ba = Signal(self._bank_bits)
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self.comb += Cat(ba, ca).eq(cba)
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else:
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ca = None
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ba = cba
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m_ca.append(ca)
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m_ba.append(ba)
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m_rca.append(rca)
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return m_ca, m_ba, m_rca
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class Initiator(Module):
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def __init__(self, generator, bus):
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self.generator = generator
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176
misoclib/mem/sdram/lasmicon/crossbar.py
Normal file
176
misoclib/mem/sdram/lasmicon/crossbar.py
Normal file
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@ -0,0 +1,176 @@
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from migen.fhdl.std import *
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from migen.genlib import roundrobin
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from migen.genlib.record import *
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from migen.genlib.misc import optree
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from misoclib.mem.sdram.bus.lasmibus import Interface
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def _getattr_all(l, attr):
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it = iter(l)
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r = getattr(next(it), attr)
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for e in it:
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if getattr(e, attr) != r:
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raise ValueError
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return r
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class Crossbar(Module):
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def __init__(self, controllers, cba_shift):
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self._controllers = controllers
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self._cba_shift = cba_shift
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self._rca_bits = _getattr_all(controllers, "aw")
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self._dw = _getattr_all(controllers, "dw")
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self._nbanks = _getattr_all(controllers, "nbanks")
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self._req_queue_size = _getattr_all(controllers, "req_queue_size")
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self._read_latency = _getattr_all(controllers, "read_latency")
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self._write_latency = _getattr_all(controllers, "write_latency")
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self._bank_bits = log2_int(self._nbanks, False)
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self._controller_bits = log2_int(len(self._controllers), False)
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self._masters = []
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def get_master(self):
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if self.finalized:
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raise FinalizeError
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lasmi_master = Interface(self._rca_bits + self._bank_bits + self._controller_bits,
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self._dw, 1, self._req_queue_size, self._read_latency, self._write_latency)
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self._masters.append(lasmi_master)
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return lasmi_master
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def do_finalize(self):
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nmasters = len(self._masters)
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m_ca, m_ba, m_rca = self._split_master_addresses(self._controller_bits,
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self._bank_bits, self._rca_bits, self._cba_shift)
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for nc, controller in enumerate(self._controllers):
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if self._controller_bits:
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controller_selected = [ca == nc for ca in m_ca]
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else:
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controller_selected = [1]*nmasters
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master_req_acks = [0]*nmasters
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master_dat_w_acks = [0]*nmasters
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master_dat_r_acks = [0]*nmasters
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rrs = [roundrobin.RoundRobin(nmasters, roundrobin.SP_CE) for n in range(self._nbanks)]
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self.submodules += rrs
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for nb, rr in enumerate(rrs):
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bank = getattr(controller, "bank"+str(nb))
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# for each master, determine if another bank locks it
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master_locked = []
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for nm, master in enumerate(self._masters):
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locked = 0
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for other_nb, other_rr in enumerate(rrs):
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if other_nb != nb:
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other_bank = getattr(controller, "bank"+str(other_nb))
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locked = locked | (other_bank.lock & (other_rr.grant == nm))
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master_locked.append(locked)
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# arbitrate
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bank_selected = [cs & (ba == nb) & ~locked for cs, ba, locked in zip(controller_selected, m_ba, master_locked)]
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bank_requested = [bs & master.stb for bs, master in zip(bank_selected, self._masters)]
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self.comb += [
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rr.request.eq(Cat(*bank_requested)),
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rr.ce.eq(~bank.stb & ~bank.lock)
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]
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# route requests
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self.comb += [
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bank.adr.eq(Array(m_rca)[rr.grant]),
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bank.we.eq(Array(self._masters)[rr.grant].we),
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bank.stb.eq(Array(bank_requested)[rr.grant])
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]
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master_req_acks = [master_req_ack | ((rr.grant == nm) & bank_selected[nm] & bank.req_ack)
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for nm, master_req_ack in enumerate(master_req_acks)]
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master_dat_w_acks = [master_dat_w_ack | ((rr.grant == nm) & bank.dat_w_ack)
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for nm, master_dat_w_ack in enumerate(master_dat_w_acks)]
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master_dat_r_acks = [master_dat_r_ack | ((rr.grant == nm) & bank.dat_r_ack)
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for nm, master_dat_r_ack in enumerate(master_dat_r_acks)]
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for nm, master_dat_w_ack in enumerate(master_dat_w_acks):
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for i in range(self._write_latency):
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new_master_dat_w_ack = Signal()
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self.sync += new_master_dat_w_ack.eq(master_dat_w_ack)
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master_dat_w_ack = new_master_dat_w_ack
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master_dat_w_acks[nm] = master_dat_w_ack
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for nm, master_dat_r_ack in enumerate(master_dat_r_acks):
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for i in range(self._read_latency):
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new_master_dat_r_ack = Signal()
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self.sync += new_master_dat_r_ack.eq(master_dat_r_ack)
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master_dat_r_ack = new_master_dat_r_ack
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master_dat_r_acks[nm] = master_dat_r_ack
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self.comb += [master.req_ack.eq(master_req_ack) for master, master_req_ack in zip(self._masters, master_req_acks)]
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self.comb += [master.dat_w_ack.eq(master_dat_w_ack) for master, master_dat_w_ack in zip(self._masters, master_dat_w_acks)]
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self.comb += [master.dat_r_ack.eq(master_dat_r_ack) for master, master_dat_r_ack in zip(self._masters, master_dat_r_acks)]
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# route data writes
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controller_selected_wl = controller_selected
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for i in range(self._write_latency):
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n_controller_selected_wl = [Signal() for i in range(nmasters)]
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self.sync += [n.eq(o) for n, o in zip(n_controller_selected_wl, controller_selected_wl)]
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controller_selected_wl = n_controller_selected_wl
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dat_w_maskselect = []
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dat_we_maskselect = []
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for master, selected in zip(self._masters, controller_selected_wl):
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o_dat_w = Signal(self._dw)
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o_dat_we = Signal(self._dw//8)
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self.comb += If(selected,
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o_dat_w.eq(master.dat_w),
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o_dat_we.eq(master.dat_we)
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)
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dat_w_maskselect.append(o_dat_w)
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dat_we_maskselect.append(o_dat_we)
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self.comb += [
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controller.dat_w.eq(optree("|", dat_w_maskselect)),
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controller.dat_we.eq(optree("|", dat_we_maskselect))
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]
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# route data reads
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if self._controller_bits:
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for master in self._masters:
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controller_sel = Signal(self._controller_bits)
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for nc, controller in enumerate(self._controllers):
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for nb in range(nbanks):
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bank = getattr(controller, "bank"+str(nb))
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self.comb += If(bank.stb & bank.ack, controller_sel.eq(nc))
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for i in range(self._read_latency):
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n_controller_sel = Signal(self._controller_bits)
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self.sync += n_controller_sel.eq(controller_sel)
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controller_sel = n_controller_sel
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self.comb += master.dat_r.eq(Array(self._controllers)[controller_sel].dat_r)
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else:
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self.comb += [master.dat_r.eq(self._controllers[0].dat_r) for master in self._masters]
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def _split_master_addresses(self, controller_bits, bank_bits, rca_bits, cba_shift):
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m_ca = [] # controller address
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m_ba = [] # bank address
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m_rca = [] # row and column address
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for master in self._masters:
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cba = Signal(self._controller_bits + self._bank_bits)
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rca = Signal(self._rca_bits)
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cba_upper = cba_shift + controller_bits + bank_bits
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self.comb += cba.eq(master.adr[cba_shift:cba_upper])
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if cba_shift < self._rca_bits:
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if cba_shift:
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self.comb += rca.eq(Cat(master.adr[:cba_shift], master.adr[cba_upper:]))
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else:
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self.comb += rca.eq(master.adr[cba_upper:])
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else:
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self.comb += rca.eq(master.adr[:cba_shift])
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if self._controller_bits:
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ca = Signal(self._controller_bits)
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ba = Signal(self._bank_bits)
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self.comb += Cat(ba, ca).eq(cba)
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else:
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ca = None
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ba = cba
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m_ca.append(ca)
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m_ba.append(ba)
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m_rca.append(rca)
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return m_ca, m_ba, m_rca
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@ -4,6 +4,7 @@ from migen.bus import wishbone, csr
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from misoclib.mem.sdram.bus import dfi, lasmibus
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from misoclib.mem.sdram.phy import dfii
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from misoclib.mem.sdram import minicon, lasmicon
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from misoclib.mem.sdram.lasmicon import crossbar
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from misoclib.mem.sdram.frontend import memtest, wishbone2lasmi
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from misoclib.soc import SoC, mem_decoder
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@ -47,7 +48,7 @@ class SDRAMSoC(SoC):
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self.submodules.lasmicon = lasmicon.LASMIcon(phy_settings, sdram_geom, sdram_timing)
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self.submodules.dficon1 = dfi.Interconnect(self.lasmicon.dfi, self.dfii.slave)
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self.submodules.lasmixbar = lasmibus.Crossbar([self.lasmicon.lasmic], self.lasmicon.nrowbits)
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self.submodules.lasmixbar = crossbar.Crossbar([self.lasmicon.lasmic], self.lasmicon.nrowbits)
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if self.with_memtest:
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self.submodules.memtest_w = memtest.MemtestWriter(self.lasmixbar.get_master())
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