soc/sdram: add capability to share L2 cache in multi-CPU SoCs
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@ -26,6 +26,13 @@ class SDRAMSoC(SoC):
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else:
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self.sdram_controller_settings = sdram_controller_settings
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self._sdram_phy_registered = False
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self._wb_sdram_ifs = []
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self._wb_sdram = wishbone.Interface()
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def add_wb_sdram_if(self, interface):
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if self.finalized:
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raise FinalizeError
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self._wb_sdram_ifs.append(interface)
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def register_sdram_phy(self, phy):
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if self._sdram_phy_registered:
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@ -47,6 +54,11 @@ class SDRAMSoC(SoC):
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main_ram_size = min(main_ram_size, 256*1024*1024)
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l2_size = self.sdram_controller_settings.l2_size
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# add a wishbone interface to the DRAM
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wb_sdram = wishbone.Interface()
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self.add_wb_sdram_if(wb_sdram)
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self.register_mem("main_ram", self.mem_map["main_ram"], wb_sdram, main_ram_size)
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# LASMICON frontend
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if isinstance(self.sdram_controller_settings, LASMIconSettings):
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if self.sdram_controller_settings.with_bandwidth:
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@ -57,9 +69,8 @@ class SDRAMSoC(SoC):
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self.submodules.memtest_r = memtest.MemtestReader(self.sdram.crossbar.get_master())
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if l2_size:
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sdram_bus = wishbone.Interface()
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lasmim = self.sdram.crossbar.get_master()
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l2_cache = wishbone.Cache(l2_size//4, sdram_bus, wishbone.Interface(lasmim.dw))
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l2_cache = wishbone.Cache(l2_size//4, self._wb_sdram, wishbone.Interface(lasmim.dw))
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# XXX Vivado ->2015.1 workaround, Vivado is not able to map correctly our L2 cache.
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# Issue is reported to Xilinx and should be fixed in next releases (2015.2?).
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# Remove this workaround when fixed by Xilinx.
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@ -70,13 +81,11 @@ class SDRAMSoC(SoC):
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else:
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self.submodules.l2_cache = l2_cache
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self.submodules.wishbone2lasmi = wishbone2lasmi.WB2LASMI(self.l2_cache.slave, lasmim)
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self.register_mem("main_ram", self.mem_map["main_ram"], sdram_bus, main_ram_size)
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# MINICON frontend
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elif isinstance(self.sdram_controller_settings, MiniconSettings):
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sdram_bus = wishbone.Interface()
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if l2_size:
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l2_cache = wishbone.Cache(l2_size//4, sdram_bus, self.sdram.controller.bus)
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l2_cache = wishbone.Cache(l2_size//4, self._wb_sdram, self.sdram.controller.bus)
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# XXX Vivado ->2015.1 workaround, Vivado is not able to map correctly our L2 cache.
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# Issue is reported to Xilinx and should be fixed in next releases (2015.2?).
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# Remove this workaround when fixed by Xilinx.
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@ -87,11 +96,14 @@ class SDRAMSoC(SoC):
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else:
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self.submodules.l2_cache = l2_cache
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else:
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self.submodules.converter = wishbone.Converter(sdram_bus, self.sdram.controller.bus)
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self.register_mem("main_ram", self.mem_map["main_ram"], sdram_bus, main_ram_size)
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self.submodules.converter = wishbone.Converter(self._wb_sdram, self.sdram.controller.bus)
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def do_finalize(self):
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if not self.integrated_main_ram_size:
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if not self._sdram_phy_registered:
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raise FinalizeError("Need to call SDRAMSoC.register_sdram_phy()")
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# arbitrate wishbone interfaces to the DRAM
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self.submodules.wb_sdram_con = wishbone.Arbiter(self._wb_sdram_ifs,
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self._wb_sdram)
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SoC.do_finalize(self)
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