Hardware/litex
1
0
Fork 0
mirror of https://github.com/enjoy-digital/litex.git synced 2025-01-04 09:52:26 -05:00
Code Issues Projects Releases Packages Wiki Activity

genlib/fifo: support RecordP

Browse source
This commit is contained in:
Sebastien Bourdeauducq 2013-10-21 22:30:06 +02:00
parent 018afe57ef
commit c0d2b5a789
1 changed files with 7 additions and 7 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

14
migen/genlib/fifo.py
View file

@ -19,18 +19,18 @@ class _FIFOInterface:
self.re = Signal()
self.readable = Signal() # not empty
if isinstance(width_or_layout, list):
self.din = Record(width_or_layout)
self.dout = Record(width_or_layout)
self.din_bits = self.din.raw_bits()
self.dout_bits = self.dout.raw_bits()
self.width = layout_len(width_or_layout)
else:
if isinstance(width_or_layout, (int, tuple)):
self.din = Signal(width_or_layout)
self.dout = Signal(width_or_layout)
self.din_bits = self.din
self.dout_bits = self.dout
self.width = width_or_layout
else:
self.din = Record(width_or_layout)
self.dout = Record(width_or_layout)
self.din_bits = self.din.raw_bits()
self.dout_bits = self.dout.raw_bits()
self.width = layout_len(width_or_layout)
class SyncFIFO(Module, _FIFOInterface):
def __init__(self, width_or_layout, depth):