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board/targets/nexys4ddr: use MT47H64M16

This commit is contained in:
Florent Kermarrec 2018-02-06 19:17:54 +01:00
parent 95ebba428c
commit c14502807e
1 changed files with 2 additions and 4 deletions
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6
litex/boards/targets/nexys4ddr.py
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@ -11,7 +11,7 @@ from litex.soc.integration.soc_core import mem_decoder
from litex.soc.integration.soc_sdram import * from litex.soc.integration.soc_sdram import *
from litex.soc.integration.builder import * from litex.soc.integration.builder import *
from litedram.modules import MT41K256M16 from litedram.modules import MT47H64M16
from litedram.phy import a7ddrphy from litedram.phy import a7ddrphy
@ -94,9 +94,7 @@ class BaseSoC(SoCSDRAM):
# sdram # sdram
self.submodules.ddrphy = a7ddrphy.A7DDRPHY(platform.request("ddram")) self.submodules.ddrphy = a7ddrphy.A7DDRPHY(platform.request("ddram"))
self.add_constant("READ_LEVELING_BITSLIP", 3) sdram_module = MT47H64M16(self.clk_freq, "1:4")
self.add_constant("READ_LEVELING_DELAY", 14)
sdram_module = MT41K256M16(self.clk_freq, "1:4")
self.register_sdram(self.ddrphy, self.register_sdram(self.ddrphy,
sdram_module.geom_settings, sdram_module.geom_settings,
sdram_module.timing_settings) sdram_module.timing_settings)