vexiiriscv add video support
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@ -59,6 +59,7 @@ class VexiiRiscv(CPU):
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with_axi3 = False
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jtag_tap = False
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jtag_instruction = False
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vexii_video = []
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vexii_args = ""
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@ -137,6 +138,7 @@ class VexiiRiscv(CPU):
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cpu_group.add_argument("--l2-ways", default=0, help="VexiiRiscv L2 ways, default 8.")
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cpu_group.add_argument("--l2-self-flush", default=None, help="VexiiRiscv L2 ways will self flush on from,to,cycles")
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cpu_group.add_argument("--with-axi3", action="store_true", help="mbus will be axi3 instead of axi4")
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cpu_group.add_argument("--vexii-video", action="append", default=[], help="Add the memory coherent video controller")
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@ -200,6 +202,7 @@ class VexiiRiscv(CPU):
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VexiiRiscv.l2_ways = args.l2_ways
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if args.l2_self_flush:
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VexiiRiscv.l2_self_flush = args.l2_self_flush
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VexiiRiscv.vexii_video = args.vexii_video
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def __init__(self, platform, variant):
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@ -306,6 +309,31 @@ class VexiiRiscv(CPU):
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o_dma_bus_rlast = dma_bus.r.last,
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)
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for video in VexiiRiscv.vexii_video:
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args = {}
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for i, val in enumerate(video.split(",")):
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name, value = val.split("=")
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args.update({name: value})
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name = args["name"]
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clk = Signal()
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hsync = Signal()
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vsync = Signal()
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color_en = Signal()
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color = Signal(16)
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setattr(self, name + "_clk", clk)
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setattr(self, name + "_hsync", hsync)
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setattr(self, name + "_vsync", vsync)
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setattr(self, name + "_color_en", color_en)
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setattr(self, name + "_color", color)
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self.cpu_params["o_" + name + "_clk"] = clk
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self.cpu_params["o_" + name + "_hSync"] = hsync
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self.cpu_params["o_" + name + "_vSync"] = vsync
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self.cpu_params["o_" + name + "_colorEn"] = color_en
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self.cpu_params["o_" + name + "_color"] = color
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def set_reset_address(self, reset_address):
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VexiiRiscv.reset_address = reset_address
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VexiiRiscv.vexii_args += f" --reset-vector {reset_address}"
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@ -327,6 +355,8 @@ class VexiiRiscv(CPU):
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md5_hash.update(str(VexiiRiscv.with_axi3).encode('utf-8'))
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md5_hash.update(str(VexiiRiscv.memory_regions).encode('utf-8'))
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md5_hash.update(str(VexiiRiscv.vexii_args).encode('utf-8'))
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md5_hash.update(str(VexiiRiscv.vexii_video).encode('utf-8'))
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# md5_hash.update(str(VexiiRiscv.internal_bus_width).encode('utf-8'))
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@ -361,6 +391,9 @@ class VexiiRiscv(CPU):
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gen_args.append(f"--with-dma")
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if(VexiiRiscv.with_axi3) :
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gen_args.append(f"--with-axi3")
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for arg in VexiiRiscv.vexii_video:
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gen_args.append(f"--video {arg}")
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cmd = f"""cd {ndir} && sbt "runMain vexiiriscv.soc.litex.SocGen {" ".join(gen_args)}\""""
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print("VexiiRiscv generation command :")
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@ -469,7 +502,12 @@ class VexiiRiscv(CPU):
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if soc.get_build_name() == "sim":
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self.comb += If(debug_ndmreset_rise, soc.crg.cd_sys.rst.eq(1))
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else:
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if hasattr(soc.crg, "rst"):
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self.comb += If(debug_ndmreset_rise, soc.crg.rst.eq(1))
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elif hasattr(soc.crg.pll, "reset"):
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self.comb += If(debug_ndmreset_rise, soc.crg.pll.reset.eq(1))
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else:
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raise Exception("Pll has no reset ?")
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self.soc_bus = soc.bus # FIXME: Save SoC Bus instance to retrieve the final mem layout on finalization.
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@ -482,6 +520,7 @@ class VexiiRiscv(CPU):
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id_width = 8,
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version = "axi3" if VexiiRiscv.with_axi3 else "axi4"
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)
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self.mBus_awallStrb = Signal()
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self.memory_buses.append(mbus)
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self.comb += mbus.aw.cache.eq(0xF)
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@ -507,7 +546,7 @@ class VexiiRiscv(CPU):
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o_mBus_awlen = mbus.aw.len,
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o_mBus_awsize = mbus.aw.size,
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o_mBus_awburst = mbus.aw.burst,
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o_mBus_awallStrb = Open(),
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o_mBus_awallStrb = self.mBus_awallStrb,
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# W Channel.
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o_mBus_wvalid = mbus.w.valid,
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i_mBus_wready = mbus.w.ready,
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@ -573,6 +612,10 @@ class VexiiRiscv(CPU):
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mode += "c" if region.cached else ""
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VexiiRiscv.memory_regions.append( (region.origin, region.size, mode, bus) )
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from litex.build.efinix import EfinixPlatform
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if isinstance(self.platform, EfinixPlatform):
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VexiiRiscv.vexii_args = "--mmu-sync-read " + VexiiRiscv.vexii_args
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self.generate_netlist_name()
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# Do verilog instance.
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