Revert "migen: create VerilogConvert and EDIFConvert classes and return it with convert functions"

This reverts commit f03aa76292.

mibuild/generic_platform.py

@@ -268,17 +268,17 @@ class GenericPlatform:
 	def _get_source(self, fragment, gen_fn):
 		if not isinstance(fragment, _Fragment):
 			fragment = fragment.get_fragment()
-		# generate source and namespace
+		# generate source
-		convert = gen_fn(fragment)
+		src, vns = gen_fn(fragment)
-		return str(convert), convert.ns
+		return src, vns
 
 	def get_verilog(self, fragment, **kwargs):
 		return self._get_source(fragment, lambda f: verilog.convert(f, self.constraint_manager.get_io_signals(),
-				create_clock_domains=False, **kwargs))
+				return_ns=True, create_clock_domains=False, **kwargs))
 
 	def get_edif(self, fragment, cell_library, vendor, device, **kwargs):
 		return self._get_source(fragment, lambda f: edif.convert(f, self.constraint_manager.get_io_signals(),
-				cell_library, vendor, device, **kwargs))
+				cell_library, vendor, device, return_ns=True, **kwargs))
 
 	def build(self, fragment):
 		raise NotImplementedError("GenericPlatform.build must be overloaded")

migen/fhdl/edif.py

@@ -182,13 +182,7 @@ def _generate_connections(f, ios, ns):
 		r[io].append(_NetBranch(portname=io, instancename=""))
 	return r
 
-class EDIFConvert:
+def convert(f, ios, cell_library, vendor, device, name="top", return_ns=False):
-	def __init__(self, f, ios, cell_library, vendor, device, name="top"):
-		self.cell_library
-		self.vendor = vendor
-		self.device = device
-		self.name = name
-
 	if not isinstance(f, _Fragment):
 		f = f.get_fragment()
 	if f.comb != [] or f.sync != {}:
@@ -200,18 +194,8 @@ class EDIFConvert:
 	instances = _generate_instances(f, ns)
 	inouts = _generate_ios(f, ios, ns)
 	connections = _generate_connections(f, ios, ns)
-
+	r =  _write_edif(cells, inouts, instances, connections, cell_library, name, device, vendor)
-		self.f = f
+	if return_ns:
-		self.ios = ios
+		return r, ns
-		self.cells = cells
+	else:
-		self.ns = ns
+		return r
-		self.instances = instances
-		self.inouts = inouts
-		self.connections = connections
-
-	def __str__(self):
-		return _write_edif(self.cells, self.inouts, self.instances, self.connections,
-			self.cell_library, self.name, self.device, self.vendor)
-
-def convert(f, ios, cell_library, vendor, device, name="top", return_ns=False):
-	return EDIFConvert(f, ios, cell_library, vendor, device, name, return_ns)

migen/fhdl/verilog.py

@@ -266,15 +266,11 @@ def _printspecials(overrides, specials, ns):
 		r += pr
 	return r
 
-class VerilogConvert:
+def convert(f, ios=None, name="top",
-	def __init__(self, f, ios=None, name="top",
+  return_ns=False,
   special_overrides=dict(),
   create_clock_domains=True,
   display_run=False):
-		self.name = name
-		self.special_overrides = special_overrides
-		self.display_run = display_run
-
 	if not isinstance(f, _Fragment):
 		f = f.get_fragment()
 	if ios is None:
@@ -301,22 +297,14 @@ class VerilogConvert:
 		| list_special_ios(f, True, True, True) \
 		| ios)
 
-		self.f = f
-		self.ios = ios
-		self.ns = ns
-		self.lowered_specials = lowered_specials
-
-	def __str__(self):
 	r = "/* Machine-generated using Migen */\n"
-		r += _printheader(self.f, self.ios, self.name, self.ns)
+	r += _printheader(f, ios, name, ns)
-		r += _printcomb(self.f, self.ns, self.display_run)
+	r += _printcomb(f, ns, display_run)
-		r += _printsync(self.f, self.ns)
+	r += _printsync(f, ns)
-		r += _printspecials(self.special_overrides, self.f.specials - self.lowered_specials, self.ns)
+	r += _printspecials(special_overrides, f.specials - lowered_specials, ns)
 	r += "endmodule\n"
-		return r
 
-def convert(f, ios=None, name="top",
+	if return_ns:
-  special_overrides=dict(),
+		return r, ns
-  create_clock_domains=True,
+	else:
-  display_run=False):
+		return r
-	return VerilogConvert(f, ios, name, special_overrides, create_clock_domains, display_run)

migen/sim/generic.py

@@ -87,17 +87,16 @@ class Simulator:
 		c_top = self.top_level.get(sockaddr)
 
 		fragment = fragment + _Fragment(clock_domains=top_level.clock_domains)
-		verilog_convert = verilog.convert(fragment,
+		c_fragment, self.namespace = verilog.convert(fragment,
 			ios=self.top_level.ios,
 			name=self.top_level.dut_type,
 			return_ns=True,
 			**vopts)
-		c_dut, self.namespace = str(verilog_convert), verilog_convert.ns
 
 		self.cycle_counter = -1
 
 		self.sim_runner = sim_runner
-		self.sim_runner.start(c_top, c_dut)
+		self.sim_runner.start(c_top, c_fragment)
 		self.ipc.accept()
 		reply = self.ipc.recv()
 		assert(isinstance(reply, MessageTick))