Hardware
/
litex
mirror of https://github.com/enjoy-digital/litex.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Use add_etherbone in simulation 

Fixes not working analyzer example from wiki
This commit is contained in:
developandplay 2021-05-26 23:18:22 +02:00 committed by GitHub
parent 5fd215fe3a
commit c17421bccb
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
1 changed files with 4 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
litex/tools/litex_sim.py
View File

@ -262,15 +262,11 @@ class SimSoC(SoCCore):
elif with_etherbone:
# Ethernet PHY
self.submodules.ethphy = LiteEthPHYModel(self.platform.request("eth", 0)) # FIXME
# Ethernet Core
ethcore = LiteEthUDPIPCore(self.ethphy,
mac_address = etherbone_mac_address,
self.add_etherbone(
phy = self.ethphy,
ip_address = etherbone_ip_address,
clk_freq = sys_clk_freq)
self.submodules.ethcore = ethcore
# Etherbone
self.submodules.etherbone = LiteEthEtherbone(self.ethcore.udp, 1234, mode="master")
self.add_wb_master(self.etherbone.wishbone.bus)
mac_address = etherbone_mac_address
)
# Analyzer ---------------------------------------------------------------------------------
if with_analyzer: