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doc: update Bank description

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Sebastien Bourdeauducq 2012-02-08 19:26:56 +01:00
parent 47883675db
commit c1bff38861
1 changed files with 10 additions and 10 deletions
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doc/migen.txt
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@ -390,7 +390,7 @@ Migen Bank
========== ==========
Migen Bank is a system comparable to wishbone-gen [6], which automates Migen Bank is a system comparable to wishbone-gen [6], which automates
the creation of configuration and status register banks and the creation of configuration and status register banks and
(TODO) interrupt/event managers implemented in cores. interrupt/event managers implemented in cores.
Bank takes a description made up of a list of registers and generates Bank takes a description made up of a list of registers and generates
logic implementing it with a slave interface compatible with Migen Bus. logic implementing it with a slave interface compatible with Migen Bus.
@ -399,11 +399,11 @@ A register can be "raw", which means that the core has direct access to
it. It also means that the register width must be less or equal to the it. It also means that the register width must be less or equal to the
bus word width. In that case, the register object provides the following bus word width. In that case, the register object provides the following
signals: signals:
- dev_r, which contains the data written from the bus interface. - r, which contains the data written from the bus interface.
- dev_re, which is the strobe signal for dev_r. It is active for one - re, which is the strobe signal for r. It is active for one cycle,
cycle, after or during a write from the bus. dev_r is only valid when after or during a write from the bus. r is only valid when re is
dev_re is high. high.
- dev_w, which must provide at all times the value to be read from the - w, which must provide at all times the value to be read from the
bus. bus.
Registers that are not raw are managed by Bank and contain fields. If the Registers that are not raw are managed by Bank and contain fields. If the
@ -413,14 +413,14 @@ maximum size and implemented at consecutive bus addresses, MSB first.
Field objects have two parameters, access_bus and access_dev, determining Field objects have two parameters, access_bus and access_dev, determining
respectively the access policies for the bus and core sides. They can respectively the access policies for the bus and core sides. They can
take the values READ_ONLY, WRITE_ONLY and READ_WRITE. take the values READ_ONLY, WRITE_ONLY and READ_WRITE.
If the device can read, the field object provides the dev_r signal, which If the device can read, the field object provides the r signal, which
contains at all times the current value of the field (kept by the logic contains at all times the current value of the field (kept by the logic
generated by Bank). generated by Bank).
If the device can write, the field object provides the following signals: If the device can write, the field object provides the following signals:
- dev_w, which provides the value to be written into the field. - w, which provides the value to be written into the field.
- dev_we, which strobes the value into the field. - we, which strobes the value into the field.
Migen Flow (TODO) Migen Flow (Work in progress)
========== ==========
Many hardware acceleration problems can be expressed in the dataflow Many hardware acceleration problems can be expressed in the dataflow
paradigm, that is, using a directed graph representing the flow of data paradigm, that is, using a directed graph representing the flow of data