xilinx/clock: Add reset_buf parameter to allow using a buffer to route reset signal.

litex/build/xilinx/common.py

@@ -71,6 +71,7 @@ class XilinxAsyncResetSynchronizerImpl(Module):
         if not hasattr(async_reset, "attr"):
             i, async_reset = async_reset, Signal()
             self.comb += async_reset.eq(i)
+        rst_buf  = Signal()
         rst_meta = Signal()
         self.specials += [
             Instance("FDPE",
@@ -89,10 +90,12 @@ class XilinxAsyncResetSynchronizerImpl(Module):
                 i_CE   = 1,
                 i_C    = cd.clk,
                 i_D    = rst_meta,
-                o_Q    = cd.rst
+                o_Q    = cd.rst if getattr(cd, "rst_buf", None) is None else rst_buf
             )
         ]
-
+        # Add optional BUFG.
+        if getattr(cd, "rst_buf", None) is not None:
+            self.specials += Instance("BUFG", i_I=rst_buf,o_O= cd.rst)
 
 class XilinxAsyncResetSynchronizer:
     @staticmethod

litex/soc/cores/clock/xilinx_common.py

@@ -44,11 +44,13 @@ class XilinxClocking(LiteXModule):
         self.clkin_freq = freq
         register_clkin_log(self.logger, clkin, freq)
 
-    def create_clkout(self, cd, freq, phase=0, buf="bufg", margin=1e-2, with_reset=True, ce=None):
+    def create_clkout(self, cd, freq, phase=0, buf="bufg", margin=1e-2, with_reset=True, reset_buf=None, ce=None):
         assert self.nclkouts < self.nclkouts_max
         clkout = Signal()
         self.clkouts[self.nclkouts] = (clkout, freq, phase, margin)
         if with_reset:
+            assert reset_buf in [None, "bufg"]
+            cd.rst_buf = reset_buf # FIXME: Improve.
             self.specials += AsyncResetSynchronizer(cd, ~self.locked)
         if buf is None:
             self.comb += cd.clk.eq(clkout)