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xilinx/clock: Add reset_buf parameter to allow using a buffer to route reset signal.

This commit is contained in:
Florent Kermarrec 2023-11-07 13:21:16 +01:00
parent d0bb837b7c
commit c1e4b3a850
2 changed files with 8 additions and 3 deletions
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7
litex/build/xilinx/common.py
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@ -71,6 +71,7 @@ class XilinxAsyncResetSynchronizerImpl(Module):
if not hasattr(async_reset, "attr"): if not hasattr(async_reset, "attr"):
i, async_reset = async_reset, Signal() i, async_reset = async_reset, Signal()
self.comb += async_reset.eq(i) self.comb += async_reset.eq(i)
rst_buf = Signal()
rst_meta = Signal() rst_meta = Signal()
self.specials += [ self.specials += [
Instance("FDPE", Instance("FDPE",
@ -89,10 +90,12 @@ class XilinxAsyncResetSynchronizerImpl(Module):
i_CE = 1, i_CE = 1,
i_C = cd.clk, i_C = cd.clk,
i_D = rst_meta, i_D = rst_meta,
o_Q = cd.rst o_Q = cd.rst if getattr(cd, "rst_buf", None) is None else rst_buf
) )
] ]
# Add optional BUFG.
if getattr(cd, "rst_buf", None) is not None:
self.specials += Instance("BUFG", i_I=rst_buf,o_O= cd.rst)
class XilinxAsyncResetSynchronizer: class XilinxAsyncResetSynchronizer:
@staticmethod @staticmethod

4
litex/soc/cores/clock/xilinx_common.py
View File

@ -44,11 +44,13 @@ class XilinxClocking(LiteXModule):
self.clkin_freq = freq self.clkin_freq = freq
register_clkin_log(self.logger, clkin, freq) register_clkin_log(self.logger, clkin, freq)
def create_clkout(self, cd, freq, phase=0, buf="bufg", margin=1e-2, with_reset=True, ce=None): def create_clkout(self, cd, freq, phase=0, buf="bufg", margin=1e-2, with_reset=True, reset_buf=None, ce=None):
assert self.nclkouts < self.nclkouts_max assert self.nclkouts < self.nclkouts_max
clkout = Signal() clkout = Signal()
self.clkouts[self.nclkouts] = (clkout, freq, phase, margin) self.clkouts[self.nclkouts] = (clkout, freq, phase, margin)
if with_reset: if with_reset:
assert reset_buf in [None, "bufg"]
cd.rst_buf = reset_buf # FIXME: Improve.
self.specials += AsyncResetSynchronizer(cd, ~self.locked) self.specials += AsyncResetSynchronizer(cd, ~self.locked)
if buf is None: if buf is None:
self.comb += cd.clk.eq(clkout) self.comb += cd.clk.eq(clkout)