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s6ddrphy: drop unused outputs, shortens verilog and produces more readable warnings 

Signed-off-by: Robert Jordens <jordens@gmail.com>
This commit is contained in:
Robert Jordens 2013-11-08 00:28:50 -07:00 committed by Sebastien Bourdeauducq
parent 4fc301ceba
commit c1e5683ba2
1 changed files with 0 additions and 23 deletions
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23
misoclib/s6ddrphy/__init__.py
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@ -264,11 +264,6 @@ class S6DDRPHY(Module):
Instance.Input("SHIFTIN2", 0), Instance.Input("SHIFTIN2", 0),
Instance.Input("SHIFTIN3", 0), Instance.Input("SHIFTIN3", 0),
Instance.Input("SHIFTIN4", 0), Instance.Input("SHIFTIN4", 0),
Instance.Output("SHIFTOUT1"),
Instance.Output("SHIFTOUT2"),
Instance.Output("SHIFTOUT3"),
Instance.Output("SHIFTOUT4"),
) )
# Data deserializer # Data deserializer
@ -286,21 +281,13 @@ class S6DDRPHY(Module):
Instance.Input("IOCE", self.clk4x_rd_strb), Instance.Input("IOCE", self.clk4x_rd_strb),
Instance.Input("RST", ResetSignal()), Instance.Input("RST", ResetSignal()),
Instance.Input("CLKDIV", sys_clk), Instance.Input("CLKDIV", sys_clk),
Instance.Output("SHIFTIN"),
Instance.Input("BITSLIP", bitslip_inc), Instance.Input("BITSLIP", bitslip_inc),
Instance.Output("FABRICOUT"),
Instance.Output("Q1", d_dfi[0*nphases+0].rddata[i+d]), Instance.Output("Q1", d_dfi[0*nphases+0].rddata[i+d]),
Instance.Output("Q2", d_dfi[0*nphases+0].rddata[i]), Instance.Output("Q2", d_dfi[0*nphases+0].rddata[i]),
Instance.Output("Q3", d_dfi[0*nphases+1].rddata[i+d]), Instance.Output("Q3", d_dfi[0*nphases+1].rddata[i+d]),
Instance.Output("Q4", d_dfi[0*nphases+1].rddata[i]), Instance.Output("Q4", d_dfi[0*nphases+1].rddata[i]),
Instance.Output("DFB"),
Instance.Output("CFB0"),
Instance.Output("CFB1"),
Instance.Output("VALID"),
Instance.Output("INCDEC"),
Instance.Output("SHIFTOUT")
) )
# Data buffer # Data buffer
@ -339,22 +326,12 @@ class S6DDRPHY(Module):
Instance.Input("D3", dq_wrdata_mask[wr_bitslip+1][i]), Instance.Input("D3", dq_wrdata_mask[wr_bitslip+1][i]),
Instance.Input("D4", dq_wrdata_mask[wr_bitslip+0][i]), Instance.Input("D4", dq_wrdata_mask[wr_bitslip+0][i]),
Instance.Output("TQ"),
Instance.Input("T1"),
Instance.Input("T2"),
Instance.Input("T3"),
Instance.Input("T4"),
Instance.Input("TRAIN", 0), Instance.Input("TRAIN", 0),
Instance.Input("TCE", 0), Instance.Input("TCE", 0),
Instance.Input("SHIFTIN1", 0), Instance.Input("SHIFTIN1", 0),
Instance.Input("SHIFTIN2", 0), Instance.Input("SHIFTIN2", 0),
Instance.Input("SHIFTIN3", 0), Instance.Input("SHIFTIN3", 0),
Instance.Input("SHIFTIN4", 0), Instance.Input("SHIFTIN4", 0),
Instance.Output("SHIFTOUT1"),
Instance.Output("SHIFTOUT2"),
Instance.Output("SHIFTOUT3"),
Instance.Output("SHIFTOUT4"),
) )
# #