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interconnect/axi/axi_full: Fix AXIUpConverter compilation.

This commit is contained in:
Florent Kermarrec 2022-09-16 14:06:22 +02:00
parent 1e1e75dba7
commit c24bbedb68
1 changed files with 6 additions and 3 deletions
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9
litex/soc/interconnect/axi/axi_full.py
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@ -193,9 +193,11 @@ class AXIUpConverter(Module):
description_to = [("data", dw_to), ("strb", dw_to//8)], description_to = [("data", dw_to), ("strb", dw_to//8)],
) )
self.submodules += w_converter self.submodules += w_converter
self.comb += axi_from.w.connect(w_converter.sink, omit={"id"}) self.comb += axi_from.w.connect(w_converter.sink, omit={"id", "dest", "user"})
self.comb += w_converter.source.connect(axi_to.w) self.comb += w_converter.source.connect(axi_to.w)
self.comb += axi_to.w.id.eq(axi_from.w.id) self.comb += axi_to.w.id.eq(axi_from.w.id)
self.comb += axi_to.w.dest.eq(axi_from.w.dest)
self.comb += axi_to.w.user.eq(axi_from.w.user)
# B Channel. # B Channel.
self.comb += axi_to.b.connect(axi_from.b) self.comb += axi_to.b.connect(axi_from.b)
@ -215,11 +217,12 @@ class AXIUpConverter(Module):
description_to = [("data", dw_from)], description_to = [("data", dw_from)],
) )
self.submodules += r_converter self.submodules += r_converter
self.comb += axi_to.r.connect(r_converter.sink, omit={"id", "resp"}) self.comb += axi_to.r.connect(r_converter.sink, omit={"id", "dest", "user", "resp"})
self.comb += r_converter.source.connect(axi_from.r) self.comb += r_converter.source.connect(axi_from.r)
self.comb += axi_from.r.resp.eq(axi_to.r.resp) self.comb += axi_from.r.resp.eq(axi_to.r.resp)
self.comb += axi_from.r.id.eq(axi_to.r.id) self.comb += axi_from.r.id.eq(axi_to.r.id)
self.comb += axi_from.r.user.eq(axi_to.r.user)
self.comb += axi_from.r.dest.eq(axi_to.r.dest)
class AXIDownConverter(Module): class AXIDownConverter(Module):
def __init__(self, axi_from, axi_to): def __init__(self, axi_from, axi_to):