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soc/cores/clock: add divclk_divide/vco_margin support on S7/Ultrascale
This commit is contained in:
Florent Kermarrec
parent
f986974d60
commit
c252972bef
1 changed files with 60 additions and 52 deletions
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@ -16,7 +16,8 @@ class S7Clocking(Module, AutoCSR):
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clkfbout_mult_frange = (2, 64+1)
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clkout_divide_range = (1, 128+1)
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def __init__(self):
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def __init__(self, vco_margin=0):
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self.vco_margin = vco_margin
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self.reset = Signal()
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self.locked = Signal()
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self.clkin_freq = None
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@ -57,30 +58,32 @@ class S7Clocking(Module, AutoCSR):
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def compute_config(self):
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config = {}
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config["divclk_divide"] = 1
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for clkfbout_mult in range(*self.clkfbout_mult_frange):
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all_valid = True
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vco_freq = self.clkin_freq*clkfbout_mult
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(vco_freq_min, vco_freq_max) = self.vco_freq_range
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if vco_freq >= vco_freq_min and vco_freq <= vco_freq_max:
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for n, (clk, f, p, m) in sorted(self.clkouts.items()):
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valid = False
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for d in range(*self.clkout_divide_range):
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clk_freq = vco_freq/d
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if abs(clk_freq - f) < f*m:
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config["clkout{}_freq".format(n)] = clk_freq
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config["clkout{}_divide".format(n)] = d
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config["clkout{}_phase".format(n)] = p
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valid = True
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break
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if not valid:
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all_valid = False
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else:
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all_valid = False
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if all_valid:
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config["vco"] = vco_freq
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config["clkfbout_mult"] = clkfbout_mult
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return config
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for divclk_divide in range(*self.divclk_divide_range):
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config["divclk_divide"] = divclk_divide
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for clkfbout_mult in range(*self.clkfbout_mult_frange):
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all_valid = True
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vco_freq = self.clkin_freq*clkfbout_mult/divclk_divide
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(vco_freq_min, vco_freq_max) = self.vco_freq_range
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if (vco_freq >= vco_freq_min*(1 + self.vco_margin) and
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vco_freq <= vco_freq_max*(1 - self.vco_margin)):
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for n, (clk, f, p, m) in sorted(self.clkouts.items()):
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valid = False
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for d in range(*self.clkout_divide_range):
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clk_freq = vco_freq/d
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if abs(clk_freq - f) < f*m:
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config["clkout{}_freq".format(n)] = clk_freq
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config["clkout{}_divide".format(n)] = d
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config["clkout{}_phase".format(n)] = p
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valid = True
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break
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if not valid:
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all_valid = False
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else:
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all_valid = False
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if all_valid:
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config["vco"] = vco_freq
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config["clkfbout_mult"] = clkfbout_mult
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return config
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raise ValueError("No PLL config found")
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def expose_drp(self):
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@ -122,6 +125,7 @@ class S7PLL(S7Clocking):
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def __init__(self, speedgrade=-1):
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S7Clocking.__init__(self)
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self.divclk_divide_range = (1, 56+1)
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self.vco_freq_range = {
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-1: (800e6, 2133e6),
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-2: (800e6, 1866e6),
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@ -152,6 +156,7 @@ class S7MMCM(S7Clocking):
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def __init__(self, speedgrade=-1):
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S7Clocking.__init__(self)
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self.divclk_divide_range = (1, 106+1)
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self.clkin_freq_range = {
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-1: (10e6, 800e6),
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-2: (10e6, 933e6),
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@ -208,7 +213,8 @@ class USClocking(Module, AutoCSR):
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clkfbout_mult_frange = (2, 64+1)
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clkout_divide_range = (1, 128+1)
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def __init__(self):
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def __init__(self, vco_margin=0):
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self.vco_margin = vco_margin
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self.reset = Signal()
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self.locked = Signal()
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self.clkin_freq = None
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@ -249,30 +255,32 @@ class USClocking(Module, AutoCSR):
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def compute_config(self):
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config = {}
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config["divclk_divide"] = 1
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for clkfbout_mult in range(*self.clkfbout_mult_frange):
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all_valid = True
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vco_freq = self.clkin_freq*clkfbout_mult
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(vco_freq_min, vco_freq_max) = self.vco_freq_range
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if vco_freq >= vco_freq_min and vco_freq <= vco_freq_max:
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for n, (clk, f, p, m) in sorted(self.clkouts.items()):
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valid = False
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for d in range(*self.clkout_divide_range):
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clk_freq = vco_freq/d
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if abs(clk_freq - f) < f*m:
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config["clkout{}_freq".format(n)] = clk_freq
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config["clkout{}_divide".format(n)] = d
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config["clkout{}_phase".format(n)] = p
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valid = True
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break
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if not valid:
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all_valid = False
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else:
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all_valid = False
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if all_valid:
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config["vco"] = vco_freq
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config["clkfbout_mult"] = clkfbout_mult
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return config
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for divclk_divide in range(*self.divclk_divide_range):
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config["divclk_divide"] = divclk_divide
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for clkfbout_mult in range(*self.clkfbout_mult_frange):
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all_valid = True
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vco_freq = self.clkin_freq*clkfbout_mult/divclk_divide
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(vco_freq_min, vco_freq_max) = self.vco_freq_range
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if (vco_freq >= vco_freq_min*(1 + self.vco_margin) and
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vco_freq <= vco_freq_max*(1 - self.vco_margin)):
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for n, (clk, f, p, m) in sorted(self.clkouts.items()):
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valid = False
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for d in range(*self.clkout_divide_range):
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clk_freq = vco_freq/d
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if abs(clk_freq - f) < f*m:
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config["clkout{}_freq".format(n)] = clk_freq
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config["clkout{}_divide".format(n)] = d
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config["clkout{}_phase".format(n)] = p
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valid = True
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break
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if not valid:
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all_valid = False
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else:
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all_valid = False
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if all_valid:
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config["vco"] = vco_freq
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config["clkfbout_mult"] = clkfbout_mult
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return config
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raise ValueError("No PLL config found")
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def expose_drp(self):
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@ -313,12 +321,12 @@ class USPLL(USClocking):
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def __init__(self, speedgrade=-1):
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USClocking.__init__(self)
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self.divclk_divide_range = (1, 56+1)
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self.clkin_freq_range = {
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-1: (70e6, 800e6),
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-2: (70e6, 933e6),
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-3: (70e6, 1066e6),
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}[speedgrade]
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self.vco_freq_range = {
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-1: (600e6, 1200e6),
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-2: (600e6, 1335e6),
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@ -349,12 +357,12 @@ class USMMCM(USClocking):
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def __init__(self, speedgrade=-1):
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USClocking.__init__(self)
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self.divclk_divide_range = (1, 106+1)
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self.clkin_freq_range = {
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-1: (10e6, 800e6),
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-2: (10e6, 933e6),
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-3: (10e6, 1066e6),
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}[speedgrade]
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self.vco_freq_range = {
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-1: (600e6, 1200e6),
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-2: (600e6, 1440e6),
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