reorganize code
- use sys_clk of 166.66MHz and using it instead of sata clk. - rename clocking to CRG since it also handles resets. - create datapath and move code from gtx.
This commit is contained in:
Florent Kermarrec
parent
879478a6e4
commit
c27f24c4c0
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@ -2,10 +2,11 @@ from migen.fhdl.std import *
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from migen.flow.actor import Sink, Source
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from lib.sata.k7sataphy.std import *
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from lib.sata.k7sataphy.gtx import K7SATAPHYGTX, K7SATAPHYRXAlign
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from lib.sata.k7sataphy.gtx import K7SATAPHYRXConvert, K7SATAPHYTXConvert
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from lib.sata.k7sataphy.clocking import K7SATAPHYClocking
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from lib.sata.k7sataphy.gtx import K7SATAPHYGTX
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from lib.sata.k7sataphy.crg import K7SATAPHYCRG
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from lib.sata.k7sataphy.ctrl import K7SATAPHYHostCtrl, K7SATAPHYDeviceCtrl
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from lib.sata.k7sataphy.datapath import K7SATAPHYRXAlign
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from lib.sata.k7sataphy.datapath import K7SATAPHYRXConvert, K7SATAPHYTXConvert
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class K7SATAPHY(Module):
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def __init__(self, pads, clk_freq, host=True,):
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@ -17,7 +18,7 @@ class K7SATAPHY(Module):
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gtx.rxrate.eq(0b000),
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gtx.txrate.eq(0b000),
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]
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clocking = K7SATAPHYClocking(pads, gtx, clk_freq)
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clocking = K7SATAPHYCRG(pads, gtx, clk_freq)
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rxalign = K7SATAPHYRXAlign()
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rxconvert = K7SATAPHYRXConvert()
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txconvert = K7SATAPHYTXConvert()
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@ -24,11 +24,10 @@ class K7SATAPHYReconfig(Module):
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drp.connect(channel_drp)
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)
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class K7SATAPHYClocking(Module):
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class K7SATAPHYCRG(Module):
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def __init__(self, pads, gtx, clk_freq):
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self.reset = Signal()
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self.clock_domains.cd_sata = ClockDomain()
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self.clock_domains.cd_sata_tx = ClockDomain()
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self.clock_domains.cd_sata_rx = ClockDomain()
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@ -118,7 +117,7 @@ class K7SATAPHYClocking(Module):
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# Configuration Reset
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# After configuration, GTX resets can not be asserted for 500ns
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# After configuration, GTX resets have to stay low for at least 500ns
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# See AR43482
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reset_en = Signal()
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clk_period_ns = 1000000000/clk_freq
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@ -119,7 +119,7 @@ class K7SATAPHYHostCtrl(Module):
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txcominit_d = Signal()
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txcomwake_d = Signal()
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self.sync.sata += [
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self.sync += [
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txcominit_d.eq(txcominit),
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txcomwake_d.eq(txcomwake),
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gtx.txcominit.eq(txcominit & ~txcominit_d),
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@ -128,7 +128,7 @@ class K7SATAPHYHostCtrl(Module):
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self.comb += align_detect.eq(self.rxdata == ALIGN_VAL);
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align_timeout_cnt = Signal(16)
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self.sync.sata += \
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self.sync += \
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If(fsm.ongoing("RESET"),
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If(self.speed == 0b100,
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align_timeout_cnt.eq(us(873, "SATA3"))
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@ -142,7 +142,7 @@ class K7SATAPHYHostCtrl(Module):
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)
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self.comb += align_timeout.eq(align_timeout_cnt == 0)
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self.sync.sata += \
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self.sync += \
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If(fsm.ongoing("RESET") | fsm.ongoing("AWAIT_NO_COMINIT"),
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If(self.speed == 0b100,
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retry_cnt.eq(us(10000, "SATA3"))
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@ -155,7 +155,7 @@ class K7SATAPHYHostCtrl(Module):
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retry_cnt.eq(retry_cnt-1)
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)
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self.sync.sata += \
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self.sync += \
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If(fsm.ongoing("SEND_ALIGN"),
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If(self.rxdata[0:8] == K28_5,
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non_align_cnt.eq(non_align_cnt + 1)
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@ -250,7 +250,7 @@ class K7SATAPHYDeviceCtrl(Module):
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txcominit_d = Signal()
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txcomwake_d = Signal()
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self.sync.sata += [
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self.sync += [
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txcominit_d.eq(txcominit),
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txcomwake_d.eq(txcomwake),
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gtx.txcominit.eq(txcominit & ~txcominit_d),
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@ -259,7 +259,7 @@ class K7SATAPHYDeviceCtrl(Module):
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self.comb += align_detect.eq(self.rxdata == ALIGN_VAL);
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align_timeout_cnt = Signal(16)
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self.sync.sata += \
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self.sync += \
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If(fsm.ongoing("RESET"),
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If(self.speed == 0b100,
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align_timeout_cnt.eq(us(55, "SATA3"))
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@ -0,0 +1,103 @@
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from migen.fhdl.std import *
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from migen.actorlib.fifo import AsyncFIFO
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from migen.actorlib.structuring import Converter
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from migen.flow.actor import Sink, Source
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from lib.sata.k7sataphy.std import *
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class K7SATAPHYRXAlign(Module):
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def __init__(self, dw=16):
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self.rxdata_i = Signal(dw)
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self.rxcharisk_i = Signal(dw//8)
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self.rxdata_o = Signal(dw)
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self.rxcharisk_o = Signal(dw//8)
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###
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rxdata_r = Signal(dw)
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rxcharisk_r = Signal(dw//8)
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self.sync.sata_rx += [
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rxdata_r.eq(self.rxdata_i),
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rxcharisk_r.eq(self.rxcharisk_i)
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]
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cases = {}
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cases[1<<0] = [
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self.rxdata_o.eq(rxdata_r[0:dw]),
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self.rxcharisk_o.eq(rxcharisk_r[0:dw//8])
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]
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for i in range(1, dw//8):
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cases[1<<i] = [
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self.rxdata_o.eq(Cat(self.rxdata_i[8*i:dw], rxdata_r[0:8*i])),
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self.rxcharisk_o.eq(Cat(self.rxcharisk_i[i:dw//8], rxcharisk_r[0:i]))
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]
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self.comb += Case(rxcharisk_r, cases)
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class K7SATAPHYRXConvert(Module):
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def __init__(self):
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self.rxdata = Signal(16)
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self.rxcharisk = Signal(2)
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self.source = Source([("data", 32), ("charisk", 4)])
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###
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# convert data widths
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rx_converter = RenameClockDomains(Converter([("raw", 16+2)], [("raw", 32+4)]), "sata_rx")
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self.submodules += rx_converter
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self.comb += [
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rx_converter.sink.stb.eq(1),
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rx_converter.sink.raw.eq(Cat(self.rxdata , self.rxcharisk)),
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rx_converter.source.ack.eq(1)
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]
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# clock domain crossing
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# SATA device is supposed to lock its tx frequency to its received rx frequency, so this
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# ensure that sata_rx and sata_tx clock have the same frequency with only not the same
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# phase and thus ensute the rx_fifo will never be full.
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rx_fifo = AsyncFIFO([("raw", 36)], 16)
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self.submodules.rx_fifo = RenameClockDomains(rx_fifo, {"write": "sata_rx", "read": "sys"})
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self.comb += [
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rx_converter.source.connect(self.rx_fifo.sink),
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self.rx_fifo.source.ack.eq(1),
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]
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# rearrange data
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self.comb += [
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self.source.stb.eq(self.rx_fifo.source.stb),
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self.source.payload.data.eq(Cat(rx_fifo.source.raw[0:16], rx_fifo.source.raw[18:18+16])),
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self.source.payload.charisk.eq(Cat(rx_fifo.source.raw[16:18], rx_fifo.source.raw[18+16:18+18])),
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self.rx_fifo.source.ack.eq(self.source.ack),
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]
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class K7SATAPHYTXConvert(Module):
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def __init__(self):
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self.sink = Sink([("data", 32), ("charisk", 4)])
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self.txdata = Signal(16)
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self.txcharisk = Signal(2)
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###
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# convert data widths
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tx_converter = RenameClockDomains(Converter([("raw", 32+4)], [("raw", 16+2)]), "sata_tx")
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self.submodules += tx_converter
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self.comb += [
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Cat(self.txdata, self.txcharisk).eq(tx_converter.source.raw),
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tx_converter.source.ack.eq(1),
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]
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# clock domain crossing
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tx_fifo = AsyncFIFO([("raw", 36)], 16)
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self.submodules.tx_fifo = RenameClockDomains(tx_fifo, {"write": "sys", "read": "sata_tx"})
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self.comb += [
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tx_fifo.source.connect(tx_converter.sink),
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self.tx_fifo.sink.stb.eq(1),
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]
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# rearrange data
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self.comb += [
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self.tx_fifo.sink.stb.eq(self.sink.stb),
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self.tx_fifo.sink.raw.eq(Cat(self.sink.data[0:16], self.sink.charisk[0:2],
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self.sink.data[16:32], self.sink.charisk[2:4])),
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self.sink.ack.eq(self.tx_fifo.sink.ack),
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]
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@ -759,100 +759,3 @@ class K7SATAPHYGTX(Module):
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**gtxe2_channel_parameters
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)
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class K7SATAPHYRXAlign(Module):
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def __init__(self, dw=16):
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self.rxdata_i = Signal(dw)
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self.rxcharisk_i = Signal(dw//8)
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self.rxdata_o = Signal(dw)
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self.rxcharisk_o = Signal(dw//8)
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###
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rxdata_r = Signal(dw)
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rxcharisk_r = Signal(dw//8)
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self.sync.sata_rx += [
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rxdata_r.eq(self.rxdata_i),
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rxcharisk_r.eq(self.rxcharisk_i)
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]
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cases = {}
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cases[1<<0] = [
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self.rxdata_o.eq(rxdata_r[0:dw]),
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self.rxcharisk_o.eq(rxcharisk_r[0:dw//8])
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]
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for i in range(1, dw//8):
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cases[1<<i] = [
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self.rxdata_o.eq(Cat(self.rxdata_i[8*i:dw], rxdata_r[0:8*i])),
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self.rxcharisk_o.eq(Cat(self.rxcharisk_i[i:dw//8], rxcharisk_r[0:i]))
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]
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self.comb += Case(rxcharisk_r, cases)
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class K7SATAPHYRXConvert(Module):
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def __init__(self):
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self.rxdata = Signal(16)
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self.rxcharisk = Signal(2)
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self.source = Source([("data", 32), ("charisk", 4)])
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###
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# convert data widths
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rx_converter = RenameClockDomains(Converter([("raw", 16+2)], [("raw", 32+4)]), "sata_rx")
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self.submodules += rx_converter
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self.comb += [
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rx_converter.sink.stb.eq(1),
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rx_converter.sink.raw.eq(Cat(self.rxdata , self.rxcharisk)),
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rx_converter.source.ack.eq(1)
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]
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# clock domain crossing
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# SATA device is supposed to lock its tx frequency to its received rx frequency, so this
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# ensure that sata_rx and sata_tx clock have the same frequency with only not the same
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# phase and thus ensute the rx_fifo will never be full.
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rx_fifo = AsyncFIFO([("raw", 36)], 16)
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self.submodules.rx_fifo = RenameClockDomains(rx_fifo, {"write": "sata_rx", "read": "sata"})
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self.comb += [
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rx_converter.source.connect(self.rx_fifo.sink),
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self.rx_fifo.source.ack.eq(1),
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]
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# rearrange data
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self.comb += [
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self.source.stb.eq(self.rx_fifo.source.stb),
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self.source.payload.data.eq(Cat(rx_fifo.source.raw[0:16], rx_fifo.source.raw[18:18+16])),
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self.source.payload.charisk.eq(Cat(rx_fifo.source.raw[16:18], rx_fifo.source.raw[18+16:18+18])),
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self.rx_fifo.source.ack.eq(self.source.ack),
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]
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class K7SATAPHYTXConvert(Module):
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def __init__(self):
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self.sink = Sink([("data", 32), ("charisk", 4)])
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self.txdata = Signal(16)
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self.txcharisk = Signal(2)
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###
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# convert data widths
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tx_converter = RenameClockDomains(Converter([("raw", 32+4)], [("raw", 16+2)]), "sata_tx")
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self.submodules += tx_converter
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self.comb += [
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Cat(self.txdata, self.txcharisk).eq(tx_converter.source.raw),
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tx_converter.source.ack.eq(1),
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]
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# clock domain crossing
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tx_fifo = AsyncFIFO([("raw", 36)], 16)
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self.submodules.tx_fifo = RenameClockDomains(tx_fifo, {"write": "sata", "read": "sata_tx"})
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self.comb += [
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tx_fifo.source.connect(tx_converter.sink),
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self.tx_fifo.sink.stb.eq(1),
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]
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# rearrange data
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self.comb += [
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self.tx_fifo.sink.stb.eq(self.sink.stb),
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self.tx_fifo.sink.raw.eq(Cat(self.sink.data[0:16], self.sink.charisk[0:2],
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self.sink.data[16:32], self.sink.charisk[2:4])),
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self.sink.ack.eq(self.tx_fifo.sink.ack),
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]
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@ -30,8 +30,8 @@ class _CRG(Module):
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p_CLKFBOUT_MULT=5, p_DIVCLK_DIVIDE=1,
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i_CLKIN1=clk200_se, i_CLKFBIN=pll_fb, o_CLKFBOUT=pll_fb,
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# 125MHz
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p_CLKOUT0_DIVIDE=8, p_CLKOUT0_PHASE=0.0, o_CLKOUT0=pll_sys,
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# 166.66MHz
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p_CLKOUT0_DIVIDE=6, p_CLKOUT0_PHASE=0.0, o_CLKOUT0=pll_sys,
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p_CLKOUT1_DIVIDE=2, p_CLKOUT1_PHASE=0.0, #o_CLKOUT1=,
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@ -90,7 +90,7 @@ class TestDesign(UART2WB):
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default_platform = "kc705"
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def __init__(self, platform):
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clk_freq = 125*1000000
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clk_freq = 166666*1000
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UART2WB.__init__(self, platform, clk_freq)
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self.submodules.crg = _CRG(platform)
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