Merge pull request #1111 from mmicko/anlogic
Add initial support for Anlogic devices
This commit is contained in:
enjoy-digital
GitHub
commit
c2d6ea97fa
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#
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# This file is part of LiteX.
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#
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# Copyright (c) 2021 Miodrag Milanovic <mmicko@gmail.com>
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# Copyright (c) 2015-2021 Florent Kermarrec <florent@enjoy-digital.fr>
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# SPDX-License-Identifier: BSD-2-Clause
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import os
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import math
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import subprocess
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import datetime
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from shutil import which
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from migen.fhdl.structure import _Fragment
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from litex.build.generic_platform import *
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from litex.build import tools
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# Constraints (.adc and .sdc) ----------------------------------------------------------------------
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def _build_adc(named_sc, named_pc):
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adc = []
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flat_sc = []
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for name, pins, other, resource in named_sc:
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if len(pins) > 1:
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for i, p in enumerate(pins):
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flat_sc.append((f"{name}[{i}]", p, other))
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else:
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flat_sc.append((name, pins[0], other))
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for name, pin, other in flat_sc:
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line = f"set_pin_assignment {{{name}}} {{ LOCATION = {pin}; "
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for c in other:
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if isinstance(c, IOStandard):
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line += f" IOSTANDARD = {c.name}; "
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line += f"}}"
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adc.append(line)
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if named_pc:
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adc.extend(named_pc)
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with open("top.adc", "w") as f:
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f.write("\n".join(adc))
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def _build_sdc(clocks, vns):
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sdc = []
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for clk, period in sorted(clocks.items(), key=lambda x: x[0].duid):
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sdc.append(f"create_clock -name {vns.get_name(clk)} -period {str(period)} [get_ports {{{vns.get_name(clk)}}}]")
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with open("top.sdc", "w") as f:
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f.write("\n".join(sdc))
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# Script -------------------------------------------------------------------------------------------
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def _build_al(name, family, device, files):
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xml = []
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date = datetime.datetime.now().strftime("%Y-%m-%d %H:%M:%S")
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# Set Device.
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xml.append(f"<?xml version=\"1.0\" encoding=\"UTF-8\"?>")
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xml.append(f"<Project Version=\"1\" Path=\"...\">")
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xml.append(f" <Project_Created_Time>{date}</Project_Created_Time>")
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xml.append(f" <TD_Version>5.0.28716</TD_Version>")
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xml.append(f" <UCode>00000000</UCode>")
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xml.append(f" <Name>{name}</Name>")
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xml.append(f" <HardWare>")
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xml.append(f" <Family>{family}</Family>")
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xml.append(f" <Device>{device}</Device>")
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xml.append(f" </HardWare>")
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xml.append(f" <Source_Files>")
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xml.append(f" <Verilog>")
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# Add Sources.
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for f, typ, lib in files:
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xml.append(f" <File Path=\"{f}\">")
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xml.append(f" <FileInfo>")
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xml.append(f" <Attr Name=\"UsedInSyn\" Val=\"true\"/>")
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xml.append(f" <Attr Name=\"UsedInP&R\" Val=\"true\"/>")
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xml.append(f" <Attr Name=\"BelongTo\" Val=\"design_1\"/>")
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xml.append(f" <Attr Name=\"CompileOrder\" Val=\"1\"/>")
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xml.append(f" </FileInfo>")
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xml.append(f" </File>")
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xml.append(f" </Verilog>")
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# Add IOs Constraints.
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xml.append(f" <ADC_FILE>")
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xml.append(f" <File Path=\"top.adc\">")
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xml.append(f" <FileInfo>")
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xml.append(f" <Attr Name=\"UsedInSyn\" Val=\"true\"/>")
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xml.append(f" <Attr Name=\"UsedInP&R\" Val=\"true\"/>")
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xml.append(f" <Attr Name=\"BelongTo\" Val=\"constrain_1\"/>")
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xml.append(f" <Attr Name=\"CompileOrder\" Val=\"1\"/>")
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xml.append(f" </FileInfo>")
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xml.append(f" </File>")
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xml.append(f" </ADC_FILE>")
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xml.append(f" <SDC_FILE>")
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xml.append(f" <File Path=\"top.sdc\">")
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xml.append(f" <FileInfo>")
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xml.append(f" <Attr Name=\"UsedInSyn\" Val=\"true\"/>")
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xml.append(f" <Attr Name=\"UsedInP&R\" Val=\"true\"/>")
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xml.append(f" <Attr Name=\"BelongTo\" Val=\"constrain_1\"/>")
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xml.append(f" <Attr Name=\"CompileOrder\" Val=\"2\"/>")
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xml.append(f" </FileInfo>")
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xml.append(f" </File>")
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xml.append(f" </SDC_FILE>")
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xml.append(f" </Source_Files>")
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xml.append(f" <FileSets>")
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xml.append(f" <FileSet Name=\"constrain_1\" Type=\"ConstrainFiles\">")
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xml.append(f" </FileSet>")
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xml.append(f" <FileSet Name=\"design_1\" Type=\"DesignFiles\">")
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xml.append(f" </FileSet>")
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xml.append(f" </FileSets>")
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xml.append(f" <TOP_MODULE>")
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xml.append(f" <LABEL></LABEL>")
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xml.append(f" <MODULE>{name}</MODULE>")
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xml.append(f" <CREATEINDEX>auto</CREATEINDEX>")
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xml.append(f" </TOP_MODULE>")
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xml.append(f" <Property>")
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xml.append(f" </Property>")
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xml.append(f" <Device_Settings>")
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xml.append(f" </Device_Settings>")
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xml.append(f" <Configurations>")
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xml.append(f" </Configurations>")
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xml.append(f" <Project_Settings>")
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xml.append(f" <Step_Last_Change>{date}</Step_Last_Change>")
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xml.append(f" <Current_Step>0</Current_Step>")
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xml.append(f" <Step_Status>true</Step_Status>")
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xml.append(f" </Project_Settings>")
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xml.append(f"</Project>")
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# Generate .al.
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with open(name + ".al", "w") as f:
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f.write("\n".join(xml))
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def _build_tcl(name, architecture, package):
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tcl = []
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# Set Device.
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tcl.append(f"import_device {architecture}.db -package {package}")
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# Add project.
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tcl.append(f"open_project {name}.al")
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# Rlaborate
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tcl.append(f"elaborate -top {name}")
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# Add IOs Constraints.
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tcl.append("read_adc top.adc")
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tcl.append("optimize_rtl")
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# Add SDC Constraints.
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tcl.append("read_sdc top.sdc")
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# Perform PnR
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tcl.append("optimize_gate")
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tcl.append("legalize_phy_inst")
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tcl.append("place")
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tcl.append("route")
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tcl.append(f"bitgen -bit \"{name}.bit\" -version 0X00 -g ucode:000000000000000000000000")
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# Generate .tcl.
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with open("run.tcl", "w") as f:
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f.write("\n".join(tcl))
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# TangDinastyToolchain -----------------------------------------------------------------------------------
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def parse_device(device):
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devices = {
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"EG4S20BG256" :[ "eagle_s20", "EG4", "BG256" ],
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}
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if device not in devices.keys():
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raise ValueError("Invalid device {}".format(device))
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(architecture, family, package) = devices[device]
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return (architecture, family, package)
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class TangDinastyToolchain:
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attr_translate = {}
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def __init__(self):
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self.clocks = dict()
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def build(self, platform, fragment,
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build_dir = "build",
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build_name = "top",
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run = True,
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**kwargs):
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# Create build directory.
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cwd = os.getcwd()
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os.makedirs(build_dir, exist_ok=True)
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os.chdir(build_dir)
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# Finalize design
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if not isinstance(fragment, _Fragment):
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fragment = fragment.get_fragment()
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platform.finalize(fragment)
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# Generate verilog
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v_output = platform.get_verilog(fragment, name=build_name, **kwargs)
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named_sc, named_pc = platform.resolve_signals(v_output.ns)
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v_file = build_name + ".v"
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v_output.write(v_file)
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platform.add_source(v_file)
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# Generate constraints file.
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# IOs (.adc).
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_build_adc(
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named_sc = named_sc,
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named_pc = named_pc
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)
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# Timings (.sdc)
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_build_sdc(
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clocks = self.clocks,
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vns = v_output.ns
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)
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architecture, family, package = parse_device(platform.device)
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# Generate project file (.al)
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al = _build_al(
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name = build_name,
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family = family,
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device = platform.device,
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files = platform.sources)
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# Generate build script (.tcl)
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script = _build_tcl(
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name = build_name,
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architecture = architecture,
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package = package)
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# Run
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if run:
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if which("td") is None:
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msg = "Unable to find Tang Dinasty toolchain, please:\n"
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msg += "- Add Tang Dinasty toolchain to your $PATH."
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raise OSError(msg)
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if subprocess.call(["td", "run.tcl"]) != 0:
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raise OSError("Error occured during Tang Dinasty's script execution.")
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os.chdir(cwd)
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return v_output.ns
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def add_period_constraint(self, platform, clk, period):
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clk.attr.add("keep")
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period = math.floor(period*1e3)/1e3 # round to lowest picosecond
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if clk in self.clocks:
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if period != self.clocks[clk]:
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raise ValueError("Clock already constrained to {:.2f}ns, new constraint to {:.2f}ns"
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.format(self.clocks[clk], period))
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self.clocks[clk] = period
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@ -0,0 +1,51 @@
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#
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# This file is part of LiteX.
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#
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# Copyright (c) 2021 Miodrag Milanovic <mmicko@gmail.com>
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# Copyright (c) 2015-2021 Florent Kermarrec <florent@enjoy-digital.fr>
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# SPDX-License-Identifier: BSD-2-Clause
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from migen.fhdl.module import Module
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from litex.build.io import *
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# Anlogic AsyncResetSynchronizer ---------------------------------------------------------------------
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class AnlogicAsyncResetSynchronizerImpl(Module):
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def __init__(self, cd, async_reset):
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rst1 = Signal()
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self.specials += [
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Instance("AL_MAP_SEQ",
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p_DFFMODE = "FF",
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p_REGSET = "SET",
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p_SRMUX = "SR",
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p_SRMODE = "ASYNC",
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i_ce = 1,
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i_d = 0,
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i_sr = async_reset,
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i_clk = cd.clk,
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o_q = rst1),
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Instance("AL_MAP_SEQ",
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p_DFFMODE = "FF",
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p_REGSET = "SET",
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p_SRMUX = "SR",
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p_SRMODE = "ASYNC",
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i_ce = 1,
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i_d = rst1,
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i_sr = async_reset,
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i_clk = cd.clk,
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o_q = cd.rst)
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]
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class AnlogicAsyncResetSynchronizer:
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@staticmethod
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def lower(dr):
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return AnlogicAsyncResetSynchronizerImpl(dr.cd, dr.async_reset)
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# Anlogic Special Overrides --------------------------------------------------------------------------
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anlogic_special_overrides = {
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AsyncResetSynchronizer: AnlogicAsyncResetSynchronizer,
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}
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@ -0,0 +1,38 @@
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#
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# This file is part of LiteX.
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#
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# Copyright (c) 2021 Miodrag Milanovic <mmicko@gmail.com>
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# Copyright (c) 2015-2021 Florent Kermarrec <florent@enjoy-digital.fr>
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# SPDX-License-Identifier: BSD-2-Clause
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import os
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from litex.build.generic_platform import GenericPlatform
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from litex.build.anlogic import common, anlogic
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# AnlogicPlatform -----------------------------------------------------------------------------------
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class AnlogicPlatform(GenericPlatform):
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bitstream_ext = ".fs"
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def __init__(self, device, *args, toolchain="td", **kwargs):
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GenericPlatform.__init__(self, device, *args, **kwargs)
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if toolchain == "td":
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self.toolchain = anlogic.TangDinastyToolchain()
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else:
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raise ValueError("Unknown toolchain")
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def get_verilog(self, *args, special_overrides=dict(), **kwargs):
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so = dict(common.anlogic_special_overrides)
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so.update(special_overrides)
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return GenericPlatform.get_verilog(self, *args,
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special_overrides = so,
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attr_translate = self.toolchain.attr_translate,
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**kwargs)
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def build(self, *args, **kwargs):
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return self.toolchain.build(self, *args, **kwargs)
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def add_period_constraint(self, clk, period):
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if clk is None: return
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self.toolchain.add_period_constraint(self, clk, period)
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