soc/cores/cpu/minerva: add self.reset to i_rst

2019-12-13 23:44:07 +01:00 · 2019-12-13 23:44:07 +01:00 · c34255d2ab
parent 8b6f9e0a2c
commit c34255d2ab
1 changed files with 1 additions and 1 deletions
--- a/litex/soc/cores/cpu/minerva/core.py
+++ b/litex/soc/cores/cpu/minerva/core.py
@ -48,7 +48,7 @@ class Minerva(CPU):
        self.cpu_params = dict(
            # clock / reset
            i_clk=ClockSignal(),
-            i_rst=ResetSignal(),
+            i_rst=ResetSignal() | self.reset,

            # interrupts
            i_timer_interrupt    = 0,