interconnect/stream: add missing part of Demultiplexer

This commit is contained in:
Florent Kermarrec 2015-10-05 00:10:55 +02:00
parent af3723db14
commit c38d8175b7
1 changed files with 7 additions and 0 deletions

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@ -142,3 +142,10 @@ class Demultiplexer(Module):
setattr(self, "source"+str(i), source)
sources.append(source)
self.sel = Signal(max=n)
# # #
cases = {}
for i, source in enumerate(sources):
cases[i] = Record.connect(self.sink, source)
self.comb += Case(self.sel, cases)