interconnect/stream: add missing part of Demultiplexer
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@ -142,3 +142,10 @@ class Demultiplexer(Module):
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setattr(self, "source"+str(i), source)
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setattr(self, "source"+str(i), source)
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sources.append(source)
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sources.append(source)
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self.sel = Signal(max=n)
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self.sel = Signal(max=n)
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# # #
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cases = {}
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for i, source in enumerate(sources):
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cases[i] = Record.connect(self.sink, source)
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self.comb += Case(self.sel, cases)
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