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add L2 cache size in identifier + function to flush L2

This commit is contained in:
Sebastien Bourdeauducq 2013-11-16 16:27:21 +01:00
parent 940341b4bf
commit c3d0985fb2
4 changed files with 23 additions and 3 deletions
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6
misoclib/identifier/__init__.py
View File

@ -4,10 +4,11 @@ from migen.bank.description import *
from misoclib.identifier import git
class Identifier(Module, AutoCSR):
def __init__(self, sysid, frequency, revision=None):
def __init__(self, sysid, frequency, l2_size, revision=None):
self._r_sysid = CSRStatus(16)
self._r_revision = CSRStatus(32)
self._r_frequency = CSRStatus(32)
self._r_l2_size = CSRStatus(8)
###
@ -17,5 +18,6 @@ class Identifier(Module, AutoCSR):
self.comb += [
self._r_sysid.status.eq(sysid),
self._r_revision.status.eq(revision),
self._r_frequency.status.eq(frequency)
self._r_frequency.status.eq(frequency),
self._r_l2_size.status.eq(l2_size)
]

1
software/include/base/system.h
View File

@ -7,6 +7,7 @@ extern "C" {
void flush_cpu_icache(void);
void flush_cpu_dcache(void);
void flush_l2_cache(void);
#ifdef __cplusplus
}

16
software/libbase/system.c
View File

@ -2,6 +2,8 @@
#include <uart.h>
#include <system.h>
#include <hw/mem.h>
#include <hw/csr.h>
void flush_cpu_icache(void)
{
@ -21,3 +23,17 @@ void flush_cpu_dcache(void)
"nop\n"
);
}
void flush_l2_cache(void)
{
unsigned int l2_nwords;
unsigned int i;
register unsigned int addr;
register unsigned int dummy;
l2_nwords = 1 << (identifier_l2_size_read() - 2);
for(i=0;i<2*l2_nwords;i++) {
addr = SDRAM_BASE + i*4;
__asm__ volatile("lw %0, (%1+0)\n":"=r"(dummy):"r"(addr));
}
}

3
top.py
View File

@ -158,7 +158,8 @@ class SoC(Module):
#
self.submodules.crg = mxcrg.MXCRG(MXClockPads(platform), clk_freq)
self.submodules.uart = uart.UART(platform.request("serial"), clk_freq, baud=115200)
self.submodules.identifier = identifier.Identifier(self.known_platform_id[platform_name], int(clk_freq))
self.submodules.identifier = identifier.Identifier(self.known_platform_id[platform_name], int(clk_freq),
log2_int(l2_size))
self.submodules.timer0 = timer.Timer()
if platform_name == "mixxeo":
self.submodules.leds = gpio.GPIOOut(platform.request("user_led"))