cpu/rocket: rework variant naming convention
The naming convention for LiteX Rocket variants has become overly complex. Simplify it while at the same time adding more flexibility. There is a new set of instances of varying main RAM memory bus port width (1x (64bit), 2x (128bit), 4x (256bit), and 8x (512bit)), of each of the following principal LiteX specific Rocket models: - small: (rv64imac, no MMU, no S, no FPU) - medium: (rv64imac, adds MMU and S-mode) - linux: (rv64imafdc, adds FPU, supports linux distros) - full: (rv64imafdcbkph[+], adds hypervisor support) NOTE: before adding H support, the feature set of the old `full` model is now represented by the `linux` model. The old `linux` did not use to have an FPU, and is now available as `medium`. In addition to the range of memory port widths, each model will be instantiated in 1, 2, 4, and 8 core variants. The naming convention is `LitexConfig_<model>_<num_cores>_<mem_width>`. E.g. `LitexConfig_full_8_2` for an 8-core full model with a 128bit main RAM AXI port. On the build command line, this example would look like: ... --cpu-type rocket --cpu-variant full \ --cpu-num-cores 8 --cpu-mem-width 2 \ ... There are a total of 4 * 4 * 4 = 64 (sub-)variants: each of the four principal models can be fitted with one of four core counts, and one of four memory bus widths. Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
This commit is contained in:
Gabriel Somlo
parent
1c43a71970
commit
c3e93620ec
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@ -30,6 +30,7 @@
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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import os
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import logging
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from migen import *
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@ -44,67 +45,6 @@ from litex.soc.integration.soc import SoCRegion
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from litex.soc.cores.cpu import CPU, CPU_GCC_TRIPLE_RISCV64
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# Variants -----------------------------------------------------------------------------------------
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CPU_VARIANTS = {
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"standard" : "freechips.rocketchip.system.LitexConfig",
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"linux" : "freechips.rocketchip.system.LitexLinuxConfig",
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"linux4" : "freechips.rocketchip.system.LitexLinux4Config",
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"linuxd" : "freechips.rocketchip.system.LitexLinuxDConfig",
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"linux2d" : "freechips.rocketchip.system.LitexLinux2DConfig",
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"linuxq" : "freechips.rocketchip.system.LitexLinuxQConfig",
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"linux2q" : "freechips.rocketchip.system.LitexLinux2QConfig",
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"full" : "freechips.rocketchip.system.LitexFullConfig",
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"fulld" : "freechips.rocketchip.system.LitexFullDConfig",
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"full4d" : "freechips.rocketchip.system.LitexFull4DConfig",
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"fullq" : "freechips.rocketchip.system.LitexFullQConfig",
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"full4q" : "freechips.rocketchip.system.LitexFull4QConfig",
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"fullo" : "freechips.rocketchip.system.LitexFullOConfig",
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"full4o" : "freechips.rocketchip.system.LitexFull4OConfig",
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"full8o" : "freechips.rocketchip.system.LitexFull8OConfig",
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}
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# GCC Flags-----------------------------------------------------------------------------------------
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GCC_FLAGS = {
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"standard" : "-march=rv64i2p0_mac -mabi=lp64 ",
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"linux" : "-march=rv64i2p0_mac -mabi=lp64 ",
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"linux4" : "-march=rv64i2p0_mac -mabi=lp64 ",
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"linuxd" : "-march=rv64i2p0_mac -mabi=lp64 ",
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"linux2d" : "-march=rv64i2p0_mac -mabi=lp64 ",
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"linuxq" : "-march=rv64i2p0_mac -mabi=lp64 ",
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"linux2q" : "-march=rv64i2p0_mac -mabi=lp64 ",
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"full" : "-march=rv64i2p0_mafdc -mabi=lp64 ",
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"fulld" : "-march=rv64i2p0_mafdc -mabi=lp64 ",
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"full4d" : "-march=rv64i2p0_mafdc -mabi=lp64 ",
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"fullq" : "-march=rv64i2p0_mafdc -mabi=lp64 ",
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"full4q" : "-march=rv64i2p0_mafdc -mabi=lp64 ",
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"fullo" : "-march=rv64i2p0_mafdc -mabi=lp64 ",
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"full4o" : "-march=rv64i2p0_mafdc -mabi=lp64 ",
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"full8o" : "-march=rv64i2p0_mafdc -mabi=lp64 ",
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}
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# CPU Params ----------------------------------------------------------------------------------
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CPU_PARAMS = {
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# Variant : (mem_dw, mmio_dw, num_cores)
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"standard" : ( 64, 64, 1),
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"linux" : ( 64, 64, 1),
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"linux4" : ( 64, 64, 4),
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"linuxd" : ( 128, 64, 1),
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"linux2d" : ( 128, 64, 2),
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"linuxq" : ( 256, 64, 1),
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"linux2q" : ( 256, 64, 2),
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"full" : ( 64, 64, 1),
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"fulld" : ( 128, 64, 1),
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"full4d" : ( 128, 64, 4),
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"fullq" : ( 256, 64, 1),
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"full4q" : ( 256, 64, 4),
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"fullo" : ( 512, 64, 1),
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"full4o" : ( 512, 64, 4),
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"full8o" : ( 512, 64, 8),
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}
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# Rocket ------------------------------------------------------------------------------------------
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class Rocket(CPU):
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@ -112,7 +52,7 @@ class Rocket(CPU):
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family = "riscv"
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name = "rocket"
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human_name = "RocketRV64[imac]"
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variants = CPU_VARIANTS
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variants = ["small", "medium", "linux", "full"]
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data_width = 64
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endianness = "little"
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gcc_triple = CPU_GCC_TRIPLE_RISCV64
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@ -120,13 +60,38 @@ class Rocket(CPU):
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nop = "nop"
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io_regions = {0x1200_0000: 0x7000_0000} # Origin, Length.
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# Default parameters.
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cpu_num_cores = 1
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cpu_mem_width = 1
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# Command line configuration arguments.
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@staticmethod
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def args_fill(parser):
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cpu_group = parser.add_argument_group(title="CPU options")
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cpu_group.add_argument("--cpu-num-cores", default=1, help="Number of cores (1, 2, 4, 8).", type=int)
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cpu_group.add_argument("--cpu-mem-width", default=1, help="Width of memory port (1, 2, 4, 8).", type=int)
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@staticmethod
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def args_read(args):
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logger = logging.getLogger("RocketArgs")
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if int(args.cpu_num_cores) in [1, 2, 4, 8]:
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Rocket.cpu_num_cores = int(args.cpu_num_cores)
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else:
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logger.error("Invalid '--cpu-num-cores {}' (should be 1, 2, 4, or 8)".format(args.cpu_num_cores))
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quit()
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if int(args.cpu_mem_width) in [1, 2, 4, 8]:
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Rocket.cpu_mem_width = int(args.cpu_mem_width)
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else:
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logger.error("Invalid '--cpu-mem-width {}' (should be 1, 2, 4, or 8)".format(args.cpu_mem_width))
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quit()
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# Arch.
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@staticmethod
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def get_arch(variant):
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if "full" in variant:
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return "rv64imafdc"
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if variant in ["linux", "full"]:
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return "rv64i2p0_mafdc"
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else:
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return "rv64imac"
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return "rv64i2p0_mac"
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# Memory Mapping.
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@property
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@ -146,19 +111,20 @@ class Rocket(CPU):
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@property
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def gcc_flags(self):
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flags = "-mno-save-restore "
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flags += GCC_FLAGS[self.variant]
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flags += f"-march={self.get_arch(self.variant)} -mabi=lp64 "
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flags += "-D__rocket__ "
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flags += "-mcmodel=medany"
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return flags
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def __init__(self, platform, variant="standard"):
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def __init__(self, platform, variant="linux"):
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self.platform = platform
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self.variant = variant
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self.reset = Signal()
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self.interrupt = Signal(8)
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mem_dw, mmio_dw, num_cores = CPU_PARAMS[self.variant]
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mem_dw = 64 * Rocket.cpu_mem_width
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mmio_dw = 64
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self.mem_axi = mem_axi = axi.AXIInterface(data_width=mem_dw, address_width=32, id_width=4)
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self.mmio_axi = mmio_axi = axi.AXIInterface(data_width=mmio_dw, address_width=32, id_width=4)
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@ -329,7 +295,7 @@ class Rocket(CPU):
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o_l2_frontend_bus_axi4_0_r_bits_last = l2fb_axi.r.last,
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)
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# additional per-core debug signals:
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self.cpu_params.update({'i_resetctrl_hartIsInReset_%s'%i : Open() for i in range(num_cores)})
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self.cpu_params.update({'i_resetctrl_hartIsInReset_%s'%i : Open() for i in range(Rocket.cpu_num_cores)})
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# Adapt AXI interfaces to Wishbone.
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mmio_a2w = axi.AXI2Wishbone(mmio_axi, mmio_wb, base_address=0)
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@ -346,12 +312,14 @@ class Rocket(CPU):
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assert reset_address == 0x1000_0000, "cpu_reset_addr hardcoded in during elaboration!"
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@staticmethod
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def add_sources(platform, variant="standard"):
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def add_sources(platform, variant):
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pfx = "freechips.rocketchip.system.LitexConfig"
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fname = f"{pfx}_{variant}_{Rocket.cpu_num_cores}_{Rocket.cpu_mem_width}"
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vdir = get_data_mod("cpu", "rocket").data_location
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platform.add_sources(
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os.path.join(vdir, "generated-src"),
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CPU_VARIANTS[variant] + ".v",
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CPU_VARIANTS[variant] + ".behav_srams.v",
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f"{fname}.v",
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f"{fname}.behav_srams.v",
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)
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platform.add_sources(
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os.path.join(vdir, "vsrc"),
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@ -361,16 +329,13 @@ class Rocket(CPU):
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)
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def add_soc_components(self, soc):
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# Get CPU Params.
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mem_dw, mmio_dw, num_cores = CPU_PARAMS[self.variant]
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# Add OpenSBI/PLIC/CLINT regions.
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soc.bus.add_region("opensbi", SoCRegion(origin=self.mem_map["main_ram"] + 0x0000_0000, size=0x20_0000, cached=False, linker=True))
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soc.bus.add_region("plic", SoCRegion(origin=soc.mem_map.get("plic"), size=0x40_0000, cached=True, linker=True))
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soc.bus.add_region("clint", SoCRegion(origin=soc.mem_map.get("clint"), size= 0x1_0000, cached=True, linker=True))
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# Define number of CPUs
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soc.add_config("CPU_COUNT", num_cores)
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soc.add_config("CPU_COUNT", Rocket.cpu_num_cores)
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soc.add_config("CPU_ISA", self.get_arch(self.variant))
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soc.add_config("CPU_MMU", "sv39")
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