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stream/ClockDomainCrossing: Add Python's ID to local clock domain names to fix build with anonymous modules.

This commit is contained in:
Florent Kermarrec 2022-04-01 15:56:49 +02:00
parent 80b309d1a4
commit c400479174
1 changed files with 6 additions and 4 deletions
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10
litex/soc/interconnect/stream.py
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@ -245,6 +245,7 @@ class ClockDomainCrossing(Module):
def __init__(self, layout, cd_from="sys", cd_to="sys", depth=None, with_common_rst=True): def __init__(self, layout, cd_from="sys", cd_to="sys", depth=None, with_common_rst=True):
self.sink = Endpoint(layout) self.sink = Endpoint(layout)
self.source = Endpoint(layout) self.source = Endpoint(layout)
# # # # # #
# Same Clk Domains. # Same Clk Domains.
@ -255,17 +256,18 @@ class ClockDomainCrossing(Module):
else: else:
if with_common_rst: if with_common_rst:
# Create intermediate Clk Domains and generate a common Rst. # Create intermediate Clk Domains and generate a common Rst.
_cd_id = id(self) # FIXME: Improve, used to allow build with anonymous modules.
_cd_rst = Signal() _cd_rst = Signal()
_cd_from = ClockDomain("from") _cd_from = ClockDomain(f"from{_cd_id}")
_cd_to = ClockDomain("to") _cd_to = ClockDomain(f"to{_cd_id}")
self.clock_domains += _cd_from, _cd_to self.clock_domains += _cd_from, _cd_to
self.comb += [ self.comb += [
_cd_from.clk.eq(ClockSignal(cd_from)), _cd_from.clk.eq(ClockSignal(cd_from)),
_cd_to.clk.eq( ClockSignal(cd_to)), _cd_to.clk.eq( ClockSignal(cd_to)),
_cd_rst.eq(ResetSignal(cd_from) | ResetSignal(cd_to)) _cd_rst.eq(ResetSignal(cd_from) | ResetSignal(cd_to))
] ]
cd_from = "from" cd_from = _cd_from.name
cd_to = "to" cd_to = _cd_to.name
# Use common Rst on both Clk Domains (through AsyncResetSynchronizer). # Use common Rst on both Clk Domains (through AsyncResetSynchronizer).
self.specials += [ self.specials += [
AsyncResetSynchronizer(_cd_from, _cd_rst), AsyncResetSynchronizer(_cd_from, _cd_rst),