cpu/naxriscv Got soft jtag tap and hard jtag tap with tunneling to work on hardware
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@ -44,10 +44,13 @@ class NaxRiscv(CPU):
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# Default parameters.
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# Default parameters.
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with_fpu = False
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with_fpu = False
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with_rvc = False
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with_rvc = False
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scala_files = ["misc.scala", "fetch.scala", "frontend.scala", "branch_predictor_std.scala", "lsu.scala", "eu_2alu_1share.scala"]
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scala_args = []
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scala_files = ["gen.scala"]
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netlist_name = None
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netlist_name = None
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scala_paths = []
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scala_paths = []
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xlen = 32
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xlen = 32
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jtag_tap = False
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jtag_instruction = False
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# ABI.
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# ABI.
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@staticmethod
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@staticmethod
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@ -93,13 +96,21 @@ class NaxRiscv(CPU):
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def args_fill(parser):
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def args_fill(parser):
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cpu_group = parser.add_argument_group(title="CPU options")
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cpu_group = parser.add_argument_group(title="CPU options")
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cpu_group.add_argument("--scala-file", action="append", help="Specify the scala files used to configure NaxRiscv.")
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cpu_group.add_argument("--scala-file", action="append", help="Specify the scala files used to configure NaxRiscv.")
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cpu_group.add_argument("--scala-args", action="append", help="Add arguements for the scala run time. Ex : --scala-args 'rvc=true,mmu=false'")
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cpu_group.add_argument("--xlen", default=32, help="Specify the RISC-V data width.")
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cpu_group.add_argument("--xlen", default=32, help="Specify the RISC-V data width.")
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cpu_group.add_argument("--with-jtag-tap", action="store_true", help="Add a embedded JTAG tap for debugging")
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cpu_group.add_argument("--with-jtag-instruction", action="store_true", help="Add a JTAG instruction port which implement tunneling for debugging (TAP not included)")
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@staticmethod
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@staticmethod
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def args_read(args):
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def args_read(args):
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print(args)
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print(args)
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NaxRiscv.jtag_tap = args.with_jtag_tap
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NaxRiscv.jtag_instruction = args.with_jtag_instruction
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if args.scala_file:
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if args.scala_file:
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NaxRiscv.scala_files = args.scala_file
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NaxRiscv.scala_files = args.scala_file
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if args.scala_args:
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NaxRiscv.scala_args = args.scala_args
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print(args.scala_args)
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if args.xlen:
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if args.xlen:
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xlen = int(args.xlen)
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xlen = int(args.xlen)
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NaxRiscv.xlen = xlen
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NaxRiscv.xlen = xlen
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@ -185,6 +196,10 @@ class NaxRiscv(CPU):
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md5_hash = hashlib.md5()
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md5_hash = hashlib.md5()
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md5_hash.update(str(reset_address).encode('utf-8'))
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md5_hash.update(str(reset_address).encode('utf-8'))
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md5_hash.update(str(NaxRiscv.xlen).encode('utf-8'))
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md5_hash.update(str(NaxRiscv.xlen).encode('utf-8'))
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md5_hash.update(str(NaxRiscv.jtag_tap).encode('utf-8'))
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md5_hash.update(str(NaxRiscv.jtag_instruction).encode('utf-8'))
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for args in NaxRiscv.scala_args:
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md5_hash.update(args.encode('utf-8'))
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for file in NaxRiscv.scala_paths:
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for file in NaxRiscv.scala_paths:
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a_file = open(file, "rb")
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a_file = open(file, "rb")
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content = a_file.read()
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content = a_file.read()
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@ -214,14 +229,22 @@ class NaxRiscv(CPU):
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ndir = os.path.join(vdir, "ext", "NaxRiscv")
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ndir = os.path.join(vdir, "ext", "NaxRiscv")
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sdir = os.path.join(vdir, "ext", "SpinalHDL")
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sdir = os.path.join(vdir, "ext", "SpinalHDL")
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NaxRiscv.git_setup("NaxRiscv", ndir, "https://github.com/SpinalHDL/NaxRiscv.git" , "main", "67389bd0")
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NaxRiscv.git_setup("NaxRiscv", ndir, "https://github.com/SpinalHDL/NaxRiscv.git" , "jtag", "d5777cfe")
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NaxRiscv.git_setup("SpinalHDL", sdir, "https://github.com/SpinalHDL/SpinalHDL.git", "dev" , "62531c60")
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NaxRiscv.git_setup("SpinalHDL", sdir, "https://github.com/SpinalHDL/SpinalHDL.git", "dev" , "f8f375e2")
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gen_args = []
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gen_args = []
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gen_args.append(f"--netlist-name={NaxRiscv.netlist_name}")
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gen_args.append(f"--netlist-name={NaxRiscv.netlist_name}")
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gen_args.append(f"--netlist-directory={vdir}")
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gen_args.append(f"--netlist-directory={vdir}")
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gen_args.append(f"--reset-vector={reset_address}")
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gen_args.append(f"--reset-vector={reset_address}")
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gen_args.append(f"--xlen={NaxRiscv.xlen}")
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gen_args.append(f"--xlen={NaxRiscv.xlen}")
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for args in NaxRiscv.scala_args:
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gen_args.append(f"--scala-args={args}")
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if(NaxRiscv.jtag_tap) :
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gen_args.append(f"--with-jtag-tap")
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if(NaxRiscv.jtag_instruction) :
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gen_args.append(f"--with-jtag-instruction")
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if(NaxRiscv.jtag_tap or NaxRiscv.jtag_instruction):
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gen_args.append(f"--with-debug")
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for file in NaxRiscv.scala_paths:
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for file in NaxRiscv.scala_paths:
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gen_args.append(f"--scala-file={file}")
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gen_args.append(f"--scala-file={file}")
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@ -293,6 +316,40 @@ class NaxRiscv(CPU):
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)
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)
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soc.bus.add_slave("plic", self.plicbus, region=soc_region_cls(origin=soc.mem_map.get("plic"), size=0x400000, cached=False))
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soc.bus.add_slave("plic", self.plicbus, region=soc_region_cls(origin=soc.mem_map.get("plic"), size=0x400000, cached=False))
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if NaxRiscv.jtag_tap:
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self.jtag_tms = Signal()
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self.jtag_tck = Signal()
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self.jtag_tdi = Signal()
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self.jtag_tdo = Signal()
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self.cpu_params.update(
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i_jtag_tms=self.jtag_tms,
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i_jtag_tck=self.jtag_tck,
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i_jtag_tdi=self.jtag_tdi,
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o_jtag_tdo=self.jtag_tdo,
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)
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if NaxRiscv.jtag_instruction:
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self.jtag_clk = Signal()
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self.jtag_enable = Signal()
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self.jtag_capture = Signal()
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self.jtag_shift = Signal()
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self.jtag_update = Signal()
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self.jtag_reset = Signal()
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self.jtag_tdo = Signal()
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self.jtag_tdi = Signal()
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self.cpu_params.update(
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i_jtag_instruction_clk = self.jtag_clk,
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i_jtag_instruction_enable = self.jtag_enable,
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i_jtag_instruction_capture = self.jtag_capture,
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i_jtag_instruction_shift = self.jtag_shift,
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i_jtag_instruction_update = self.jtag_update,
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i_jtag_instruction_reset = self.jtag_reset,
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i_jtag_instruction_tdi = self.jtag_tdi,
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o_jtag_instruction_tdo = self.jtag_tdo,
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)
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# Add CLINT Bus (Wishbone Slave).
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# Add CLINT Bus (Wishbone Slave).
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self.clintbus = clintbus = axi.AXILiteInterface(address_width=32, data_width=32)
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self.clintbus = clintbus = axi.AXILiteInterface(address_width=32, data_width=32)
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self.cpu_params.update(
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self.cpu_params.update(
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