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gen/fhdl/verilog: set direction to io signals

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This commit is contained in:
Florent Kermarrec 2018-10-29 11:41:04 +01:00
parent 49dab3b448
commit c506c9752c
1 changed files with 3 additions and 0 deletions
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3
litex/gen/fhdl/verilog.py
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@ -207,13 +207,16 @@ def _printheader(f, ios, name, ns, attr_translate,
if attr: if attr:
r += "\t" + attr r += "\t" + attr
if sig in inouts: if sig in inouts:
sig.direction = "inout"
r += "\tinout " + _printsig(ns, sig) r += "\tinout " + _printsig(ns, sig)
elif sig in targets: elif sig in targets:
sig.direction = "output"
if sig in wires: if sig in wires:
r += "\toutput " + _printsig(ns, sig) r += "\toutput " + _printsig(ns, sig)
else: else:
r += "\toutput reg " + _printsig(ns, sig) r += "\toutput reg " + _printsig(ns, sig)
else: else:
sig.direction = "input"
r += "\tinput " + _printsig(ns, sig) r += "\tinput " + _printsig(ns, sig)
r += "\n);\n\n" r += "\n);\n\n"
for sig in sorted(sigs - ios, key=lambda x: x.duid): for sig in sorted(sigs - ios, key=lambda x: x.duid):