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gen/fhdl/verilog: set direction to io signals
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1 changed files with 3 additions and 0 deletions
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@ -207,13 +207,16 @@ def _printheader(f, ios, name, ns, attr_translate,
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if attr:
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r += "\t" + attr
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if sig in inouts:
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sig.direction = "inout"
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r += "\tinout " + _printsig(ns, sig)
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elif sig in targets:
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sig.direction = "output"
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if sig in wires:
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r += "\toutput " + _printsig(ns, sig)
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else:
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r += "\toutput reg " + _printsig(ns, sig)
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else:
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sig.direction = "input"
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r += "\tinput " + _printsig(ns, sig)
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r += "\n);\n\n"
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for sig in sorted(sigs - ios, key=lambda x: x.duid):
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