soc/cores/hyperbus: Add automatic read burst detection.
This commit is contained in:
Florent Kermarrec
parent
3bde3e9848
commit
c554752e8a
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@ -319,6 +319,7 @@ class HyperRAMCore(LiteXModule):
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self.bus_dat_w = bus_dat_w = Signal(32)
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self.burst_w = burst_w = Signal()
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self.burst_r = burst_r = Signal()
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self.burst_r_first = burst_r_first = Signal()
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# PHY.
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# ----
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@ -425,8 +426,9 @@ class HyperRAMCore(LiteXModule):
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If(reg.stb & ~reg.we,
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NextState("REG-READ")
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).Else(
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If(bus.we,
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bus_latch.eq(1),
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NextValue(burst_r_first, 1),
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If(bus.we,
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NextState("DAT-WRITE")
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).Else(
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NextState("DAT-READ")
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@ -470,7 +472,7 @@ class HyperRAMCore(LiteXModule):
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bus_dat_w.eq(bus.dat_w),
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)
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]
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self.comb += If(bus_latch, bus.ack.eq(1))
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self.comb += If(bus_latch, bus.ack.eq(bus.we))
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self.comb += burst_w.eq(
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# Notified Incrementing Burst.
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(bus_cti == 0b010) |
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@ -500,16 +502,21 @@ class HyperRAMCore(LiteXModule):
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# Data Read State.
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self.comb += burst_r.eq(
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# Notified Incrementing Burst.
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(bus.cti == 0b10)
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(bus_cti == 0b10) |
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# Detected Incrementing Burst.
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((bus.we == bus_we) & (bus.adr == (bus_adr + 1))),
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)
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fsm.act("DAT-READ",
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source.valid.eq(bus.cyc & bus.stb),
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source.valid.eq(1),
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source.dat_r.eq(1),
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If(dat_rx_conv.source.valid,
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bus.ack.eq(1),
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NextValue(burst_r_first, 0),
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# Ack on first or while Incrementing Burst ongoing...
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bus.ack.eq(burst_r_first | (with_bursting & bus.cyc & bus.stb & burst_r)),
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bus.dat_r.eq(dat_rx_conv.source.dq),
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# Stay in DAT-READ while Incrementing Burst ongoing...
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If(with_bursting & bus.cyc & bus.stb & burst_r,
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# If Ack, stay in DAT-READ to anticipate next read...
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If(bus.ack,
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bus_latch.eq(1),
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NextState("DAT-READ")
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# ..else exit.
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).Else(
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@ -178,13 +178,13 @@ class TestHyperRAM(unittest.TestCase):
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self.assertEqual(dat, 0xdeadbeef)
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def hyperram_gen(dut):
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clk = "_______--__--__--__--__--__--__--__--__--__--__--__--__--__--__--__--__--_____"
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cs_n = "----______________________________________________________________________----"
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dq_oe = "______------------____________________________________________________________"
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dq_o = "000000a000048d0000000000000000000000000000000000000000000000000000000000000000"
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dq_i = "000000000000000000000000000000000000000000000000000000deadbeefcafefade00000000"
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rwds_oe = "______________________________________________________________________________"
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rwds_i = "______________________________________________________--__--__--__--__________"
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clk = "_______--__--__--__--__--__--__--__--__--__--__--__--__--__--__--__--__--__--__--_____"
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cs_n = "----______________________________________________________________________________----"
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dq_oe = "______------------____________________________________________________________________"
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dq_o = "000000a000048d000000000000000000000000000000000000000000000000000000000000000000000000"
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dq_i = "000000000000000000000000000000000000000000000000000000deadbeefcafefade0000000000000000"
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rwds_oe = "______________________________________________________________________________________"
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rwds_i = "______________________________________________________--__--__--__--__________________"
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yield
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for i in range(len(clk)):
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yield dut.pads.dq.i.eq(int(dq_i[2*(i//2):2*(i//2)+2], 16))
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@ -206,13 +206,13 @@ class TestHyperRAM(unittest.TestCase):
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self.assertEqual(dat, 0xdeadbeef)
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def hyperram_gen(dut):
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clk = "_______--__--__--__--__--__--__--__--__--__--__--__--__--__--__--__--__--__--__--_____"
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cs_n = "----______________________________________________________________________________----"
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dq_oe = "______------------____________________________________________________________________"
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dq_o = "000000a000048d000000000000000000000000000000000000000000000000000000000000000000000000"
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dq_i = "00000000000000000000000000000000000000000000000000000000000000deadbeefcafefade00000000"
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rwds_oe = "______________________________________________________________________________________"
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rwds_i = "______________________________________________________________--__--__--__--__________"
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clk = "_______--__--__--__--__--__--__--__--__--__--__--__--__--__--__--__--__--__--__--__--__--_____"
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cs_n = "----______________________________________________________________________________________----"
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dq_oe = "______------------____________________________________________________________________________"
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dq_o = "000000a000048d00000000000000000000000000000000000000000000000000000000000000000000000000000000"
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dq_i = "00000000000000000000000000000000000000000000000000000000000000deadbeefcafefade0000000000000000"
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rwds_oe = "______________________________________________________________________________________________"
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rwds_i = "______________________________________________________________--__--__--__--__________________"
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yield
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for i in range(len(clk)):
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yield dut.pads.dq.i.eq(int(dq_i[2*(i//2):2*(i//2)+2], 16))
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@ -233,14 +233,15 @@ class TestHyperRAM(unittest.TestCase):
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dat = yield from dut.bus.read(0x1234)
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self.assertEqual(dat, 0xdeadbeef)
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def hyperram_gen(dut):
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clk = "_______--__--__--__--__--__--__--__--__--__--__--__--__--__--__--__--__--__--__--__--__--_____"
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cs_n = "----______________________________________________________________________________________----"
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dq_oe = "______------------____________________________________________________________________________"
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dq_o = "000000a000048d00000000000000000000000000000000000000000000000000000000000000000000000000000000"
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dq_i = "0000000000000000000000000000000000000000000000000000000000000000000000deadbeefcafefade00000000"
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rwds_oe = "______________________________________________________________________________________________"
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rwds_i = "______________________________________________________________________--__--__--__--__________"
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clk = "_______--__--__--__--__--__--__--__--__--__--__--__--__--__--__--__--__--__--__--__--__--__--__--_____"
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cs_n = "----______________________________________________________________________________________________----"
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dq_oe = "______------------____________________________________________________________________________________"
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dq_o = "000000a000048d0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"
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dq_i = "0000000000000000000000000000000000000000000000000000000000000000000000deadbeefcafefade0000000000000000"
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rwds_oe = "______________________________________________________________________________________________________"
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rwds_i = "______________________________________________________________________--__--__--__--__________________"
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yield
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for i in range(len(clk)):
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yield dut.pads.dq.i.eq(int(dq_i[2*(i//2):2*(i//2)+2], 16))
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@ -262,13 +263,13 @@ class TestHyperRAM(unittest.TestCase):
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self.assertEqual(dat, 0xdeadbeef)
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def hyperram_gen(dut):
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clk = "_______--__--__--__--__--__--__--__--__--__--__--__--__--__-______"
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cs_n = "----________________________________________________________------"
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dq_oe = "______------------________________________________________________"
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dq_o = "000000a000048d0000000000000000000000000000000000000000000000000000"
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dq_i = "0000000000000000000000000000000000000000deadbeefcafefade0000000000"
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rwds_oe = "__________________________________________________________________"
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rwds_i = "________________________________________--__--__--__--____________"
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clk = "_______--__--__--__--__--__--__--__--__--__--__--__--__--__--__--__-______"
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cs_n = "----________________________________________________________________------"
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dq_oe = "______------------________________________________________________________"
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dq_o = "000000a000048d000000000000000000000000000000000000000000000000000000000000"
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dq_i = "0000000000000000000000000000000000000000deadbeefcafefade000000000000000000"
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rwds_oe = "__________________________________________________________________________"
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rwds_i = "________________________________________--__--__--__--____________________"
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yield
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for i in range(len(clk)):
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yield dut.pads.dq.i.eq(int(dq_i[2*(i//2):2*(i//2)+2], 16))
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