WIP AvalonMM interface and Avalon to Wishbone Bridge (#1674)
Add initial AvalonMM interface and AvalonMM2Wishbone.
This commit is contained in:
Hans Baier
GitHub
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c5c7e86cca
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# This file is part of LiteX.
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#
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# Copyright (c) 2019-2020 Florent Kermarrec <florent@enjoy-digital.fr>
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# Copyright (c) 2023 Hans Baier <hansfbaier@gmail.com>
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# SPDX-License-Identifier: BSD-2-Clause
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"""Avalon support for LiteX"""
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@ -9,6 +10,235 @@
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from migen import *
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from litex.soc.interconnect import stream
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from litex.soc.interconnect import wishbone
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_layout = [
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("address", "adr_width", DIR_M_TO_S),
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("writedata", "data_width", DIR_M_TO_S),
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("readdata", "data_width", DIR_S_TO_M),
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("readdatavalid", 1, DIR_S_TO_M),
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("byteenable", "sel_width", DIR_M_TO_S),
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("read", 1, DIR_M_TO_S),
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("write", 1, DIR_M_TO_S),
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("waitrequest", 1, DIR_S_TO_M),
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("burstbegin", 1, DIR_M_TO_S), # this is optional
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("burstcount", 8, DIR_M_TO_S),
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("chipselect", 1, DIR_M_TO_S), # this is optional
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]
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class AvalonMMInterface(Record):
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def __init__(self, data_width=32, adr_width=30, **kwargs):
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self.data_width = data_width
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if kwargs.get("adr_width", False):
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adr_width = kwargs["adr_width"] - int(log2(data_width//8))
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self.adr_width = adr_width
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Record.__init__(self, set_layout_parameters(_layout,
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adr_width = adr_width,
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data_width = data_width,
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sel_width = data_width//8))
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self.address.reset_less = True
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self.writedata.reset_less = True
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self.readdata.reset_less = True
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self.byteenable.reset_less = True
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@staticmethod
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def like(other):
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return AvalonMMInterface(len(other.writedata))
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def get_ios(self, bus_name="avl"):
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subsignals = []
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for name, width, direction in self.layout:
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subsignals.append(Subsignal(name, Pins(width)))
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ios = [(bus_name , 0) + tuple(subsignals)]
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return ios
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def connect_to_pads(self, pads, mode="master"):
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assert mode in ["slave", "master"]
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r = []
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for name, width, direction in self.layout:
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sig = getattr(self, name)
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pad = getattr(pads, name)
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if mode == "master":
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if direction == DIR_M_TO_S:
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r.append(pad.eq(sig))
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else:
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r.append(sig.eq(pad))
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else:
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if direction == DIR_S_TO_M:
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r.append(pad.eq(sig))
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else:
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r.append(sig.eq(pad))
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return r
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def bus_read(self, address, byteenable=None, burstcount=1, chipselect=None):
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if byteenable is None:
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byteenable = 2**len(self.byteenable) - 1
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yield self.address.eq(address)
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yield self.write.eq(0)
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yield self.read.eq(1)
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yield self.byteenable.eq(byteenable)
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if burstcount != 1:
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yield self.burstcount.eq(burstcount)
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if chipselect is not None:
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yield self.chipselect.eq(chipselect)
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yield
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while (yield self.waitrequest):
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yield
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yield self.read.eq(0)
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# actually don't care outside of a transaction
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# this makes the traces look neater
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yield self.byteenable.eq(0)
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if burstcount != 1:
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yield self.burstcount.eq(0)
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if chipselect is not None:
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yield self.chipselect.eq(0)
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while not (yield self.readdatavalid):
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yield
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return (yield self.readdata)
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def continue_read_burst(self):
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yield
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return (yield self.readdata)
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def bus_write(self, address, writedata, byteenable=None, chipselect=None):
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if not isinstance(writedata, list):
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writedata = [ writedata ]
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burstcount = len(writedata)
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if byteenable is None:
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byteenable = 2**len(self.byteenable) - 1
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yield self.address.eq(address)
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yield self.write.eq(1)
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yield self.read.eq(0)
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yield self.byteenable.eq(byteenable)
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if burstcount is not None:
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yield self.burstcount.eq(burstcount)
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if chipselect is not None:
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yield self.chipselect.eq(chipselect)
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for data in writedata:
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yield self.writedata.eq(data)
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yield
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while (yield self.waitrequest):
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yield
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yield self.burstcount.eq(0)
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yield self.writedata.eq(0)
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yield self.write.eq(0)
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# actually don't care outside of a transaction
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# this makes the traces look neater
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yield self.byteenable.eq(0)
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if chipselect is not None:
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yield self.chipselect.eq(0)
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class AvalonMM2Wishbone(Module):
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def __init__(self, data_width=32, address_width=32, wishbone_base_address=0x0, wishbone_extend_address_bits=0, avoid_combinatorial_loop=True):
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word_width = data_width // 8
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word_width_bits = log2_int(word_width)
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wishbone_address_width = address_width - word_width_bits + wishbone_extend_address_bits
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self.a2w_wb = wb = wishbone.Interface(data_width=data_width, adr_width=wishbone_address_width, bursting=True)
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self.a2w_avl = avl = AvalonMMInterface (data_width=data_width, adr_width=address_width)
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read_access = Signal()
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readdatavalid = Signal()
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readdata = Signal(data_width)
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last_burst_cycle = Signal()
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burst_cycle = Signal()
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burst_counter = Signal.like(avl.burstcount)
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burst_address = Signal(address_width)
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burst_read = Signal()
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burst_sel = Signal.like(avl.byteenable)
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self.sync += last_burst_cycle.eq(burst_cycle)
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# Some designs might have trouble with the combinatorial loop created
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# by wb.ack, so cut it, incurring one clock cycle of overhead on each
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# bus transaction
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if avoid_combinatorial_loop:
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self.sync += [
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If (wb.ack | wb.err, read_access.eq(0)) \
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.Elif(avl.read, read_access.eq(1)),
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readdata.eq(wb.dat_r),
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readdatavalid.eq((wb.ack | wb.err) & read_access),
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]
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else:
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self.comb += [
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read_access.eq(avl.read),
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readdata.eq(wb.dat_r),
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readdatavalid.eq((wb.ack | wb.err) & read_access),
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]
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# Wishbone -> Avalon
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self.comb += [
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avl.waitrequest.eq(~(wb.ack | wb.err) | burst_read),
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avl.readdata.eq(readdata),
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avl.readdatavalid.eq(readdatavalid),
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]
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# Avalon -> Wishbone
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self.comb += [
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# avalon is byte addresses, wishbone word addressed
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wb.adr.eq(Mux(burst_cycle & last_burst_cycle,
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burst_address, avl.address)[word_width_bits:]
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+ Constant(wishbone_base_address, (wishbone_address_width, 0))),
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wb.dat_w.eq(avl.writedata),
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wb.we.eq(avl.write),
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wb.cyc.eq(read_access | avl.write | burst_cycle),
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wb.stb.eq(read_access | avl.write),
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wb.bte.eq(Constant(0, 2)),
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]
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self.submodules.fsm = fsm = FSM(reset_state="NORMAL")
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fsm.act("NORMAL",
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burst_cycle.eq(0),
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wb.sel.eq(avl.byteenable),
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wb.cti.eq(Mux(avl.burstcount > 1,
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wishbone.CTI_BURST_INCREMENTING,
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wishbone.CTI_BURST_NONE)),
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If(~avl.waitrequest & (avl.burstcount > 1),
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burst_cycle.eq(1),
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NextValue(burst_counter, avl.burstcount - 1),
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NextValue(burst_address, avl.address + word_width),
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NextValue(burst_sel, avl.byteenable),
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If(avl.write, NextState("BURST_WRITE")),
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If(avl.read,
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NextValue(burst_read, 1),
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NextState("BURST_READ")))
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)
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fsm.act("BURST_WRITE",
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burst_cycle.eq(1),
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wb.sel.eq(burst_sel),
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wb.cti.eq(Mux(burst_counter > 1,
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wishbone.CTI_BURST_INCREMENTING,
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Mux(burst_counter == 1, wishbone.CTI_BURST_END, wishbone.CTI_BURST_NONE))),
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If(~avl.waitrequest,
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NextValue(burst_address, burst_address + word_width),
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NextValue(burst_counter, burst_counter - 1)),
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If(burst_counter == 0,
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burst_cycle.eq(0),
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wb.sel.eq(avl.byteenable),
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NextValue(burst_sel, 0),
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NextState("NORMAL"))
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)
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fsm.act("BURST_READ", # TODO
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burst_cycle.eq(1),
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wb.stb.eq(1),
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wb.sel.eq(burst_sel),
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wb.cti.eq(Mux(burst_counter > 1,
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wishbone.CTI_BURST_INCREMENTING,
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Mux(burst_counter == 1, wishbone.CTI_BURST_END, wishbone.CTI_BURST_NONE))),
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If (wb.ack,
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avl.readdatavalid.eq(1),
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NextValue(burst_address, burst_address + word_width),
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NextValue(burst_counter, burst_counter - 1)),
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If (burst_counter == 0,
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wb.cyc.eq(0),
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wb.stb.eq(0),
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wb.sel.eq(avl.byteenable),
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NextValue(burst_sel, 0),
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NextValue(burst_read, 0),
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NextState("NORMAL"))
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)
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# Avalon-ST to/from native LiteX's stream ----------------------------------------------------------
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@ -0,0 +1,72 @@
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#
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# This file is part of LiteX.
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#
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# Copyright (c) 2023 Hans Baier <hansfbaier@gmail.com>
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# SPDX-License-Identifier: BSD-2-Clause
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import unittest
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from migen import *
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from litex.soc.interconnect import wishbone, avalon
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# TestWishbone -------------------------------------------------------------------------------------
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class TestAvalon2Wishbone(unittest.TestCase):
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def test_sram(self):
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def generator(dut):
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yield from dut.avl.bus_write(0x0000, 0x01234567)
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yield from dut.avl.bus_write(0x0004, 0x89abcdef)
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yield from dut.avl.bus_write(0x0008, 0xdeadbeef)
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yield from dut.avl.bus_write(0x000c, 0xc0ffee00)
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yield from dut.avl.bus_write(0x0010, 0x76543210)
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yield
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self.assertEqual((yield from dut.avl.bus_read(0x0000)), 0x01234567)
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self.assertEqual((yield from dut.avl.bus_read(0x0004)), 0x89abcdef)
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self.assertEqual((yield from dut.avl.bus_read(0x0008)), 0xdeadbeef)
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self.assertEqual((yield from dut.avl.bus_read(0x000c)), 0xc0ffee00)
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self.assertEqual((yield from dut.avl.bus_read(0x0010)), 0x76543210)
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class DUT(Module):
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def __init__(self):
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a2w = avalon.AvalonMM2Wishbone()
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self.avl = a2w.a2w_avl
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wishbone_mem = wishbone.SRAM(32, bus=a2w.a2w_wb)
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self.submodules += a2w
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self.submodules += wishbone_mem
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dut = DUT()
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run_simulation(dut, generator(dut)) #, vcd_name="avalon.vcd")
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def test_sram_burst(self):
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def generator(dut):
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yield from dut.avl.bus_write(0x0, [0x01234567, 0x89abcdef, 0xdeadbeef, 0xc0ffee00, 0x76543210])
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yield
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self.assertEqual((yield from dut.avl.bus_read(0x0000, burstcount=5)), 0x01234567)
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self.assertEqual((yield from dut.avl.continue_read_burst()), 0x89abcdef)
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self.assertEqual((yield from dut.avl.continue_read_burst()), 0xdeadbeef)
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self.assertEqual((yield from dut.avl.continue_read_burst()), 0xc0ffee00)
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self.assertEqual((yield from dut.avl.continue_read_burst()), 0x76543210)
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yield
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yield
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yield
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yield
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self.assertEqual((yield from dut.avl.bus_read(0x0000)), 0x01234567)
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self.assertEqual((yield from dut.avl.bus_read(0x0004)), 0x89abcdef)
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self.assertEqual((yield from dut.avl.bus_read(0x0008)), 0xdeadbeef)
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self.assertEqual((yield from dut.avl.bus_read(0x000c)), 0xc0ffee00)
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self.assertEqual((yield from dut.avl.bus_read(0x0010)), 0x76543210)
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yield
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yield
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class DUT(Module):
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def __init__(self):
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a2w = avalon.AvalonMM2Wishbone()
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self.avl = a2w.a2w_avl
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wishbone_mem = wishbone.SRAM(32, bus=a2w.a2w_wb)
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self.submodules += a2w
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self.submodules += wishbone_mem
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dut = DUT()
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run_simulation(dut, generator(dut)) #, vcd_name="avalon_burst.vcd")
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