ahb: Add addressing property and different address shift in AHB2Wishbone when Wishbone is byte/word addressed.
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@ -28,6 +28,7 @@ class Interface(Record):
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"""Sets up the AHB interface signals for master and slave."""
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"""Sets up the AHB interface signals for master and slave."""
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adr_width = 32
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adr_width = 32
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data_width = 32
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data_width = 32
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addressing = "byte"
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master_signals = [
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master_signals = [
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("addr", adr_width),
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("addr", adr_width),
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("burst", 3),
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("burst", 3),
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@ -56,22 +57,25 @@ class AHB2Wishbone(LiteXModule):
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It takes as input an AHB interface and a Wishbone interface and does the conversion.
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It takes as input an AHB interface and a Wishbone interface and does the conversion.
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"""
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"""
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def __init__(self, ahb, wishbone):
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def __init__(self, ahb, wishbone):
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wishbone_adr_shift = log2_int(ahb.data_width // 8)
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# Parameters/Checks.
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wishbone_adr_shift = {
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"word" : log2_int(ahb.data_width//8),
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"byte" : 0
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}[wishbone.addressing]
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assert ahb.data_width == wishbone.data_width
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assert ahb.data_width == wishbone.data_width
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assert ahb.adr_width == wishbone.adr_width + wishbone_adr_shift
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assert ahb.adr_width == wishbone.adr_width + wishbone_adr_shift
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self.comb += ahb.resp.eq(wishbone.err)
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# FSM.
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self.fsm = fsm = FSM()
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self.fsm = fsm = FSM()
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fsm.act("IDLE",
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fsm.act("IDLE",
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ahb.readyout.eq(1),
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ahb.readyout.eq(1),
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If(ahb.sel &
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If(ahb.sel &
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(ahb.size == wishbone_adr_shift) &
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(ahb.size == wishbone_adr_shift) &
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(ahb.trans == TransferType.NONSEQUENTIAL),
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(ahb.trans == TransferType.NONSEQUENTIAL),
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NextValue(wishbone.adr, ahb.addr[2:]),
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NextValue(wishbone.adr, ahb.addr[wishbone_adr_shift:]),
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NextValue(wishbone.dat_w, ahb.wdata),
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NextValue(wishbone.dat_w, ahb.wdata),
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NextValue(wishbone.we, ahb.write),
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NextValue(wishbone.we, ahb.write),
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NextValue(wishbone.sel, 2**len(wishbone.sel) - 1),
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NextValue(wishbone.sel, 2**len(wishbone.sel) - 1),
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NextState("ACT"),
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NextState("ACT"),
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)
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)
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)
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)
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@ -85,3 +89,5 @@ class AHB2Wishbone(LiteXModule):
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NextState("IDLE")
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NextState("IDLE")
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)
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)
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)
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)
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self.comb += ahb.resp.eq(wishbone.err)
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