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integration/soc/ethernet: Simplify timing constraints.

This commit is contained in:
Florent Kermarrec 2021-03-25 08:36:37 +01:00
parent e27330b0d9
commit c60938d7aa
1 changed files with 11 additions and 22 deletions
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33
litex/soc/integration/soc.py
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@ -1362,6 +1362,7 @@ class LiteXSoC(SoC):
def add_ethernet(self, name="ethmac", phy=None, phy_cd="eth", dynamic_ip=False, software_debug=False, nrxslots=2, ntxslots=2): def add_ethernet(self, name="ethmac", phy=None, phy_cd="eth", dynamic_ip=False, software_debug=False, nrxslots=2, ntxslots=2):
# Imports # Imports
from liteeth.mac import LiteEthMAC from liteeth.mac import LiteEthMAC
from liteeth.phy.model import LiteEthPHYModel
# MAC # MAC
ethmac = LiteEthMAC( ethmac = LiteEthMAC(
@ -1384,18 +1385,12 @@ class LiteXSoC(SoC):
self.irq.add(name, use_loc_if_exists=True) self.irq.add(name, use_loc_if_exists=True)
# Timing constraints # Timing constraints
if hasattr(phy, "crg"): eth_rx_clk = getattr(phy, "crg", phy).cd_eth_rx.clk
eth_rx_clk = phy.crg.cd_eth_rx.clk eth_tx_clk = getattr(phy, "crg", phy).cd_eth_tx.clk
eth_tx_clk = phy.crg.cd_eth_tx.clk if not isinstance(phy, LiteEthPHYModel):
else: self.platform.add_period_constraint(eth_rx_clk, 1e9/phy.rx_clk_freq)
eth_rx_clk = phy.cd_eth_rx.clk self.platform.add_period_constraint(eth_tx_clk, 1e9/phy.tx_clk_freq)
eth_tx_clk = phy.cd_eth_tx.clk self.platform.add_false_path_constraints(self.crg.cd_sys.clk, eth_rx_clk, eth_tx_clk)
self.platform.add_period_constraint(eth_rx_clk, 1e9/phy.rx_clk_freq)
self.platform.add_period_constraint(eth_tx_clk, 1e9/phy.tx_clk_freq)
self.platform.add_false_path_constraints(
self.crg.cd_sys.clk,
eth_rx_clk,
eth_tx_clk)
if dynamic_ip: if dynamic_ip:
self.add_constant("ETH_DYNAMIC_IP") self.add_constant("ETH_DYNAMIC_IP")
@ -1415,6 +1410,7 @@ class LiteXSoC(SoC):
from liteeth.core import LiteEthUDPIPCore from liteeth.core import LiteEthUDPIPCore
from liteeth.frontend.etherbone import LiteEthEtherbone from liteeth.frontend.etherbone import LiteEthEtherbone
from liteeth.phy.model import LiteEthPHYModel from liteeth.phy.model import LiteEthPHYModel
# Core # Core
ethcore = LiteEthUDPIPCore( ethcore = LiteEthUDPIPCore(
phy = phy, phy = phy,
@ -1438,19 +1434,12 @@ class LiteXSoC(SoC):
self.add_wb_master(etherbone.wishbone.bus) self.add_wb_master(etherbone.wishbone.bus)
# Timing constraints # Timing constraints
if hasattr(phy, "crg"): eth_rx_clk = getattr(phy, "crg", phy).cd_eth_rx.clk
eth_rx_clk = phy.crg.cd_eth_rx.clk eth_tx_clk = getattr(phy, "crg", phy).cd_eth_tx.clk
eth_tx_clk = phy.crg.cd_eth_tx.clk
else:
eth_rx_clk = phy.cd_eth_rx.clk
eth_tx_clk = phy.cd_eth_tx.clk
if not isinstance(phy, LiteEthPHYModel): if not isinstance(phy, LiteEthPHYModel):
self.platform.add_period_constraint(eth_rx_clk, 1e9/phy.rx_clk_freq) self.platform.add_period_constraint(eth_rx_clk, 1e9/phy.rx_clk_freq)
self.platform.add_period_constraint(eth_tx_clk, 1e9/phy.tx_clk_freq) self.platform.add_period_constraint(eth_tx_clk, 1e9/phy.tx_clk_freq)
self.platform.add_false_path_constraints( self.platform.add_false_path_constraints(self.crg.cd_sys.clk, eth_rx_clk, eth_tx_clk)
self.crg.cd_sys.clk,
eth_rx_clk,
eth_tx_clk)
# Add SPI Flash -------------------------------------------------------------------------------- # Add SPI Flash --------------------------------------------------------------------------------
def add_spi_flash(self, name="spiflash", mode="4x", dummy_cycles=None, clk_freq=None): def add_spi_flash(self, name="spiflash", mode="4x", dummy_cycles=None, clk_freq=None):