Avoid extra timing delays for NXLRAM path

2024-03-20 10:16:45 -06:00 · 2024-03-20 10:16:45 -06:00 · c640efcec3
parent 8f04542c15
commit c640efcec3
1 changed files with 2 additions and 2 deletions
--- a/litex/soc/cores/ram/lattice_nx.py
+++ b/litex/soc/cores/ram/lattice_nx.py
@ -79,10 +79,10 @@ class NXLRAM(LiteXModule):
                wren    = Signal()
                self.comb += [
                    datain.eq(self.bus.dat_w[32*w:32*(w+1)]),
+                    self.bus.dat_r[32*w:32*(w+1)].eq(dataout),
                    If(self.bus.adr[14:14+self.depth_cascading.bit_length()] == d,
                        cs.eq(1),
-                        wren.eq(self.bus.we & self.bus.stb & self.bus.cyc),
-                        self.bus.dat_r[32*w:32*(w+1)].eq(dataout)
+                        wren.eq(self.bus.we & self.bus.stb & self.bus.cyc)
                    ),
                ]
                lram_block = Instance("SP512K",