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Avoid extra timing delays for NXLRAM path

This commit is contained in:
jdavidberger 2024-03-20 10:16:45 -06:00 committed by Justin Berger
parent 8f04542c15
commit c640efcec3
1 changed files with 2 additions and 2 deletions
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4
litex/soc/cores/ram/lattice_nx.py
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@ -79,10 +79,10 @@ class NXLRAM(LiteXModule):
wren = Signal() wren = Signal()
self.comb += [ self.comb += [
datain.eq(self.bus.dat_w[32*w:32*(w+1)]), datain.eq(self.bus.dat_w[32*w:32*(w+1)]),
self.bus.dat_r[32*w:32*(w+1)].eq(dataout),
If(self.bus.adr[14:14+self.depth_cascading.bit_length()] == d, If(self.bus.adr[14:14+self.depth_cascading.bit_length()] == d,
cs.eq(1), cs.eq(1),
wren.eq(self.bus.we & self.bus.stb & self.bus.cyc), wren.eq(self.bus.we & self.bus.stb & self.bus.cyc)
self.bus.dat_r[32*w:32*(w+1)].eq(dataout)
), ),
] ]
lram_block = Instance("SP512K", lram_block = Instance("SP512K",