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Merge pull request #2079 from VOGL-electronic/efinix_iface_fixups 

build: efinix: ifacewriter: some fixes
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enjoy-digital 2024-09-26 17:31:53 +02:00 committed by GitHub
parent b135f71512 afcc477c4e
commit c67dfa82cc
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GPG Key ID: B5690EEEBB952194
2 changed files with 9 additions and 12 deletions
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12
litex/build/efinix/common.py
View File

@ -295,7 +295,8 @@ class EfinixDDRTristateImpl(Module):
"out_reg" : "DDIO_RESYNC", "out_reg" : "DDIO_RESYNC",
"out_clk_pin" : clk, "out_clk_pin" : clk,
"oe_reg" : "REG", "oe_reg" : "REG",
"is_inclk_inverted" : False, "in_clk_inv" : 0,
"out_clk_inv" : 0,
"drive_strength" : io_prop_dict.get("DRIVE_STRENGTH", "4") "drive_strength" : io_prop_dict.get("DRIVE_STRENGTH", "4")
} }
platform.toolchain.ifacewriter.blocks.append(block) platform.toolchain.ifacewriter.blocks.append(block)
@ -333,7 +334,8 @@ class EfinixSDRTristateImpl(EfinixDDRTristateImpl):
"out_reg" : "REG", "out_reg" : "REG",
"out_clk_pin" : clk, "out_clk_pin" : clk,
"oe_reg" : "REG", "oe_reg" : "REG",
"is_inclk_inverted" : False, "in_clk_inv" : 0,
"out_clk_inv" : 0,
"drive_strength" : io_prop_dict.get("DRIVE_STRENGTH", "4") "drive_strength" : io_prop_dict.get("DRIVE_STRENGTH", "4")
} }
platform.toolchain.ifacewriter.blocks.append(block) platform.toolchain.ifacewriter.blocks.append(block)
@ -365,7 +367,7 @@ class EfinixSDROutputImpl(Module):
"size" : 1, "size" : 1,
"out_reg" : "REG", "out_reg" : "REG",
"out_clk_pin" : clk, "out_clk_pin" : clk,
"is_inclk_inverted" : False, "out_clk_inv" : 0,
"drive_strength" : io_prop_dict.get("DRIVE_STRENGTH", "4") "drive_strength" : io_prop_dict.get("DRIVE_STRENGTH", "4")
} }
platform.toolchain.ifacewriter.blocks.append(block) platform.toolchain.ifacewriter.blocks.append(block)
@ -399,7 +401,7 @@ class EfinixDDROutputImpl(Module):
"size" : 1, "size" : 1,
"out_reg" : "DDIO_RESYNC", "out_reg" : "DDIO_RESYNC",
"out_clk_pin" : clk, "out_clk_pin" : clk,
"is_inclk_inverted" : False, "out_clk_inv" : 0,
"drive_strength" : io_prop_dict.get("DRIVE_STRENGTH", "4") "drive_strength" : io_prop_dict.get("DRIVE_STRENGTH", "4")
} }
platform.toolchain.ifacewriter.blocks.append(block) platform.toolchain.ifacewriter.blocks.append(block)
@ -460,7 +462,7 @@ class EfinixDDRInputImpl(Module):
"size" : 1, "size" : 1,
"in_reg" : "DDIO_RESYNC", "in_reg" : "DDIO_RESYNC",
"in_clk_pin" : clk, "in_clk_pin" : clk,
"is_inclk_inverted" : False "in_clk_inv" : 0
} }
platform.toolchain.ifacewriter.blocks.append(block) platform.toolchain.ifacewriter.blocks.append(block)
platform.toolchain.excluded_ios.append(platform.get_pin(i)) platform.toolchain.excluded_ios.append(platform.get_pin(i))

9
litex/build/efinix/ifacewriter.py
View File

@ -166,9 +166,6 @@ design.create("{2}", "{3}", "./../gateware", overwrite=True)
cmd += f'design.assign_pkg_pin("{name}[{i}]","{pad}")\n' cmd += f'design.assign_pkg_pin("{name}[{i}]","{pad}")\n'
if "out_reg" in block: if "out_reg" in block:
cmd += f'design.set_property("{name}","oe_REG","{block["out_reg"]}")\n'
if "oe_reg" in block:
cmd += f'design.set_property("{name}","OUT_REG","{block["out_reg"]}")\n' cmd += f'design.set_property("{name}","OUT_REG","{block["out_reg"]}")\n'
cmd += f'design.set_property("{name}","OUT_CLK_PIN","{block["out_clk_pin"]}")\n' cmd += f'design.set_property("{name}","OUT_CLK_PIN","{block["out_clk_pin"]}")\n'
if "out_delay" in block: if "out_delay" in block:
@ -176,7 +173,6 @@ design.create("{2}", "{3}", "./../gateware", overwrite=True)
if "out_clk_inv" in block: if "out_clk_inv" in block:
cmd += f'design.set_property("{name}","IS_OUTCLK_INVERTED","{block["out_clk_inv"]}")\n' cmd += f'design.set_property("{name}","IS_OUTCLK_INVERTED","{block["out_clk_inv"]}")\n'
cmd += f'design.set_property("{name}","OE_CLK_PIN_INV","{block["out_clk_inv"]}")\n'
if "in_reg" in block: if "in_reg" in block:
cmd += f'design.set_property("{name}","IN_REG","{block["in_reg"]}")\n' cmd += f'design.set_property("{name}","IN_REG","{block["in_reg"]}")\n'
@ -189,8 +185,6 @@ design.create("{2}", "{3}", "./../gateware", overwrite=True)
if "oe_reg" in block: if "oe_reg" in block:
cmd += f'design.set_property("{name}","OE_REG","{block["oe_reg"]}")\n' cmd += f'design.set_property("{name}","OE_REG","{block["oe_reg"]}")\n'
if "oe_clk_pin" in block:
cmd += f'design.set_property("{name}","OE_CLK_PIN","{block["oe_clk_pin"]}")\n'
if "drive_strength" in block: if "drive_strength" in block:
cmd += 'design.set_property("{}","DRIVE_STRENGTH","{}")\n'.format(name, block["drive_strength"]) cmd += 'design.set_property("{}","DRIVE_STRENGTH","{}")\n'.format(name, block["drive_strength"])
@ -225,6 +219,8 @@ design.create("{2}", "{3}", "./../gateware", overwrite=True)
cmd += f'design.set_property("{name}","IN_CLK_PIN","{in_clk_pin}")\n' cmd += f'design.set_property("{name}","IN_CLK_PIN","{in_clk_pin}")\n'
if "in_delay" in block: if "in_delay" in block:
cmd += f'design.set_property("{name}","INDELAY","{block["in_delay"]}")\n' cmd += f'design.set_property("{name}","INDELAY","{block["in_delay"]}")\n'
if "in_clk_inv" in block:
cmd += f'design.set_property("{name}","IS_INCLK_INVERTED","{block["in_clk_inv"]}")\n'
if prop: if prop:
for p, val in prop: for p, val in prop:
cmd += 'design.set_property("{}","{}","{}")\n'.format(name, p, val) cmd += 'design.set_property("{}","{}","{}")\n'.format(name, p, val)
@ -248,7 +244,6 @@ design.create("{2}", "{3}", "./../gateware", overwrite=True)
if "out_clk_inv" in block: if "out_clk_inv" in block:
cmd += f'design.set_property("{name}","IS_OUTCLK_INVERTED","{block["out_clk_inv"]}")\n' cmd += f'design.set_property("{name}","IS_OUTCLK_INVERTED","{block["out_clk_inv"]}")\n'
cmd += f'design.set_property("{name}","OE_CLK_PIN_INV","{block["out_clk_inv"]}")\n'
if "drive_strength" in block: if "drive_strength" in block:
cmd += 'design.set_property("{}","DRIVE_STRENGTH","{}")\n'.format(name, block["drive_strength"]) cmd += 'design.set_property("{}","DRIVE_STRENGTH","{}")\n'.format(name, block["drive_strength"])