sim: fix to support ConvOutput
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181aeb4791
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c6904f9d63
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@ -87,11 +87,11 @@ class Simulator:
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c_top = self.top_level.get(sockaddr)
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fragment = fragment + _Fragment(clock_domains=top_level.clock_domains)
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c_fragment, self.namespace = verilog.convert(fragment,
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c_fragment = verilog.convert(fragment,
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ios=self.top_level.ios,
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name=self.top_level.dut_type,
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return_ns=True,
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**vopts)
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self.namespace = c_fragment.ns
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self.cycle_counter = -1
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@ -5,10 +5,6 @@ import subprocess
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import os
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import time
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def _str2file(filename, contents):
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f = open(filename, "w")
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f.write(contents)
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f.close()
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class Runner:
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def __init__(self, options=None, extra_files=None, top_file="migensim_top.v", dut_file="migensim_dut.v", vvp_file=None, keep_files=False):
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@ -20,11 +16,14 @@ class Runner:
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self.top_file = top_file
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self.dut_file = dut_file
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self.vvp_file = vvp_file
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self.data_files = []
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self.keep_files = keep_files
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def start(self, c_top, c_dut):
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_str2file(self.top_file, c_top)
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_str2file(self.dut_file, c_dut)
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with open(self.top_file, "w") as f:
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f.write(c_top)
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c_dut.write(self.dut_file)
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self.data_files += c_dut.data_files.keys()
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subprocess.check_call(["iverilog", "-o", self.vvp_file] + self.options + [self.top_file, self.dut_file] + self.extra_files)
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self.process = subprocess.Popen(["vvp", "-mmigensim", "-Mvpi", self.vvp_file])
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@ -36,8 +35,9 @@ class Runner:
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self.process.kill()
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self.process.wait()
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if not self.keep_files:
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for f in [self.top_file, self.dut_file, self.vvp_file]:
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for f in [self.top_file, self.dut_file, self.vvp_file] + self.data_files:
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try:
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os.remove(f)
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except OSError:
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pass
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self.data_files.clear()
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