soc: cores: fix name of EHXPLLL output clock in ECP5PLL

2019-07-14 12:27:28 -07:00 · 2019-07-14 12:27:28 -07:00 · c6c743915a
parent d3aaaf5e6c
commit c6c743915a
1 changed files with 1 additions and 1 deletions
--- a/litex/soc/cores/clock.py
+++ b/litex/soc/cores/clock.py
@ -476,7 +476,7 @@ class ECP5PLL(Module):
            p_CLKI_DIV=1,
        )
        for n, (clk, f, p, m) in sorted(self.clkouts.items()):
-            n_to_l = {0: "P", 1: "S", 2: "OS2"}
+            n_to_l = {0: "P", 1: "S", 2: "S2"}
            self.params["p_CLKO{}_ENABLE".format(n_to_l[n])] = "ENABLED"
            self.params["p_CLKO{}_DIV".format(n_to_l[n])] = config["clko{}_div".format(n)]
            self.params["p_CLKO{}_FPHASE".format(n_to_l[n])] = 0