soc/cores/clocks: improve readibility
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6fcb12a98f
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c6fe3f3145
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@ -22,14 +22,14 @@ class XilinxClocking(Module, AutoCSR):
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def __init__(self, vco_margin=0):
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def __init__(self, vco_margin=0):
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self.vco_margin = vco_margin
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self.vco_margin = vco_margin
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self.reset = Signal()
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self.reset = Signal()
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self.locked = Signal()
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self.locked = Signal()
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self.clkin_freq = None
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self.clkin_freq = None
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self.vcxo_freq = None
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self.vcxo_freq = None
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self.nclkouts = 0
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self.nclkouts = 0
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self.clkouts = {}
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self.clkouts = {}
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self.config = {}
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self.config = {}
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self.params = {}
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self.params = {}
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def register_clkin(self, clkin, freq):
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def register_clkin(self, clkin, freq):
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self.clkin = Signal()
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self.clkin = Signal()
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@ -75,9 +75,9 @@ class XilinxClocking(Module, AutoCSR):
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for d in range(*self.clkout_divide_range):
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for d in range(*self.clkout_divide_range):
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clk_freq = vco_freq/d
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clk_freq = vco_freq/d
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if abs(clk_freq - f) < f*m:
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if abs(clk_freq - f) < f*m:
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config["clkout{}_freq".format(n)] = clk_freq
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config["clkout{}_freq".format(n)] = clk_freq
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config["clkout{}_divide".format(n)] = d
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config["clkout{}_divide".format(n)] = d
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config["clkout{}_phase".format(n)] = p
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config["clkout{}_phase".format(n)] = p
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valid = True
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valid = True
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break
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break
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if not valid:
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if not valid:
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@ -103,13 +103,13 @@ class XilinxClocking(Module, AutoCSR):
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drp_drdy = Signal()
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drp_drdy = Signal()
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self.params.update(
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self.params.update(
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i_DCLK=ClockSignal(),
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i_DCLK = ClockSignal(),
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i_DWE=self.drp_write.re,
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i_DWE = self.drp_write.re,
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i_DEN=self.drp_read.re | self.drp_write.re,
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i_DEN = self.drp_read.re | self.drp_write.re,
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o_DRDY=drp_drdy,
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o_DRDY = drp_drdy,
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i_DADDR=self.drp_adr.storage,
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i_DADDR = self.drp_adr.storage,
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i_DI=self.drp_dat_w.storage,
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i_DI = self.drp_dat_w.storage,
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o_DO=self.drp_dat_r.status
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o_DO = self.drp_dat_r.status
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)
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)
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self.sync += [
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self.sync += [
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If(self.drp_read.re | self.drp_write.re,
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If(self.drp_read.re | self.drp_write.re,
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@ -131,7 +131,7 @@ class S6PLL(XilinxClocking):
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def __init__(self, speedgrade=-1):
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def __init__(self, speedgrade=-1):
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XilinxClocking.__init__(self)
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XilinxClocking.__init__(self)
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self.divclk_divide_range = (1, 52 + 1)
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self.divclk_divide_range = (1, 52 + 1)
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self.vco_freq_range = {
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self.vco_freq_range = {
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-1: (400e6, 1000e6),
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-1: (400e6, 1000e6),
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-2: (400e6, 1000e6),
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-2: (400e6, 1000e6),
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-3: (400e6, 1080e6),
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-3: (400e6, 1080e6),
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@ -142,27 +142,27 @@ class S6PLL(XilinxClocking):
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config = self.compute_config()
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config = self.compute_config()
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pll_fb = Signal()
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pll_fb = Signal()
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self.params.update(
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self.params.update(
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p_SIM_DEVICE="SPARTAN6",
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p_SIM_DEVICE = "SPARTAN6",
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p_BANDWIDTH="OPTIMIZED",
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p_BANDWIDTH = "OPTIMIZED",
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p_COMPENSATION="INTERNAL",
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p_COMPENSATION = "INTERNAL",
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p_REF_JITTER=.01, p_CLK_FEEDBACK="CLKFBOUT",
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p_REF_JITTER = .01, p_CLK_FEEDBACK="CLKFBOUT",
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p_CLKIN1_PERIOD=1e9/self.clkin_freq,
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p_CLKIN1_PERIOD = 1e9/self.clkin_freq,
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p_CLKIN2_PERIOD=0.,
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p_CLKIN2_PERIOD = 0.,
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p_CLKFBOUT_MULT=config["clkfbout_mult"],
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p_CLKFBOUT_MULT = config["clkfbout_mult"],
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p_CLKFBOUT_PHASE=0.,
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p_CLKFBOUT_PHASE = 0.,
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p_DIVCLK_DIVIDE=config["divclk_divide"],
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p_DIVCLK_DIVIDE = config["divclk_divide"],
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i_CLKINSEL=1,
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i_CLKINSEL = 1,
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i_RST=self.reset,
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i_RST = self.reset,
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i_CLKIN1=self.clkin,
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i_CLKIN1 = self.clkin,
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i_CLKFBIN=pll_fb,
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i_CLKFBIN = pll_fb,
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o_CLKFBOUT=pll_fb,
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o_CLKFBOUT = pll_fb,
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o_LOCKED=self.locked,
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o_LOCKED = self.locked,
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)
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)
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for n, (clk, f, p, m) in sorted(self.clkouts.items()):
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for n, (clk, f, p, m) in sorted(self.clkouts.items()):
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self.params["p_CLKOUT{}_DIVIDE".format(n)] = config["clkout{}_divide".format(n)]
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self.params["p_CLKOUT{}_DIVIDE".format(n)] = config["clkout{}_divide".format(n)]
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self.params["p_CLKOUT{}_PHASE".format(n)] = float(config["clkout{}_phase".format(n)])
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self.params["p_CLKOUT{}_PHASE".format(n)] = float(config["clkout{}_phase".format(n)])
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self.params["p_CLKOUT{}_DUTY_CYCLE".format(n)] = 0.5
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self.params["p_CLKOUT{}_DUTY_CYCLE".format(n)] = 0.5
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self.params["o_CLKOUT{}".format(n)] = clk
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self.params["o_CLKOUT{}".format(n)] = clk
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self.specials += Instance("PLL_ADV", **self.params)
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self.specials += Instance("PLL_ADV", **self.params)
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@ -170,7 +170,7 @@ class S6DCM(XilinxClocking):
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""" single output with f_out = f_in * {2 .. 256} / {1 .. 256} """
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""" single output with f_out = f_in * {2 .. 256} / {1 .. 256} """
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nclkouts_max = 1
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nclkouts_max = 1
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clkfbout_mult_frange = (2, 256 + 1)
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clkfbout_mult_frange = (2, 256 + 1)
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clkout_divide_range = (1, 256 + 1)
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clkout_divide_range = (1, 256 + 1)
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def __init__(self, speedgrade=-1):
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def __init__(self, speedgrade=-1):
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XilinxClocking.__init__(self)
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XilinxClocking.__init__(self)
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@ -192,15 +192,15 @@ class S6DCM(XilinxClocking):
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config = self.compute_config()
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config = self.compute_config()
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clk, f, p, m = sorted(self.clkouts.items())[0][1]
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clk, f, p, m = sorted(self.clkouts.items())[0][1]
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self.params.update(
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self.params.update(
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p_CLKFX_MULTIPLY=config["clkfbout_mult"],
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p_CLKFX_MULTIPLY = config["clkfbout_mult"],
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p_CLKFX_DIVIDE=config["clkout0_divide"] * config["divclk_divide"],
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p_CLKFX_DIVIDE = config["clkout0_divide"] * config["divclk_divide"],
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p_SPREAD_SPECTRUM="NONE",
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p_SPREAD_SPECTRUM = "NONE",
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p_CLKIN_PERIOD=1e9/self.clkin_freq,
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p_CLKIN_PERIOD = 1e9/self.clkin_freq,
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i_CLKIN=self.clkin,
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i_CLKIN = self.clkin,
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i_RST=self.reset,
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i_RST = self.reset,
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i_FREEZEDCM=0,
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i_FREEZEDCM = 0,
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o_CLKFX=clk,
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o_CLKFX = clk,
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o_LOCKED=self.locked,
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o_LOCKED = self.locked,
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)
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)
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self.specials += Instance("DCM_CLKGEN", **self.params)
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self.specials += Instance("DCM_CLKGEN", **self.params)
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@ -274,14 +274,14 @@ class S7MMCM(XilinxClocking):
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else:
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else:
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self.params["p_CLKOUT{}_DIVIDE".format(n)] = config["clkout{}_divide".format(n)]
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self.params["p_CLKOUT{}_DIVIDE".format(n)] = config["clkout{}_divide".format(n)]
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self.params["p_CLKOUT{}_PHASE".format(n)] = config["clkout{}_phase".format(n)]
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self.params["p_CLKOUT{}_PHASE".format(n)] = config["clkout{}_phase".format(n)]
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self.params["o_CLKOUT{}".format(n)] = clk
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self.params["o_CLKOUT{}".format(n)] = clk
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self.specials += Instance("MMCME2_ADV", **self.params)
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self.specials += Instance("MMCME2_ADV", **self.params)
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class S7IDELAYCTRL(Module):
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class S7IDELAYCTRL(Module):
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def __init__(self, cd):
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def __init__(self, cd):
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reset_counter = Signal(4, reset=15)
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reset_counter = Signal(4, reset=15)
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ic_reset = Signal(reset=1)
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ic_reset = Signal(reset=1)
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sync = getattr(self.sync, cd.name)
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sync = getattr(self.sync, cd.name)
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sync += \
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sync += \
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If(reset_counter != 0,
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If(reset_counter != 0,
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@ -327,8 +327,8 @@ class USPLL(XilinxClocking):
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)
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)
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for n, (clk, f, p, m) in sorted(self.clkouts.items()):
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for n, (clk, f, p, m) in sorted(self.clkouts.items()):
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self.params["p_CLKOUT{}_DIVIDE".format(n)] = config["clkout{}_divide".format(n)]
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self.params["p_CLKOUT{}_DIVIDE".format(n)] = config["clkout{}_divide".format(n)]
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self.params["p_CLKOUT{}_PHASE".format(n)] = config["clkout{}_phase".format(n)]
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self.params["p_CLKOUT{}_PHASE".format(n)] = config["clkout{}_phase".format(n)]
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self.params["o_CLKOUT{}".format(n)] = clk
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self.params["o_CLKOUT{}".format(n)] = clk
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self.specials += Instance("PLLE2_ADV", **self.params)
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self.specials += Instance("PLLE2_ADV", **self.params)
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@ -367,7 +367,7 @@ class USMMCM(XilinxClocking):
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else:
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else:
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self.params["p_CLKOUT{}_DIVIDE".format(n)] = config["clkout{}_divide".format(n)]
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self.params["p_CLKOUT{}_DIVIDE".format(n)] = config["clkout{}_divide".format(n)]
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self.params["p_CLKOUT{}_PHASE".format(n)] = config["clkout{}_phase".format(n)]
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self.params["p_CLKOUT{}_PHASE".format(n)] = config["clkout{}_phase".format(n)]
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self.params["o_CLKOUT{}".format(n)] = clk
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self.params["o_CLKOUT{}".format(n)] = clk
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self.specials += Instance("MMCME2_ADV", **self.params)
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self.specials += Instance("MMCME2_ADV", **self.params)
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@ -383,9 +383,10 @@ class USIDELAYCTRL(Module):
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ic_reset.eq(0)
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ic_reset.eq(0)
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)
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)
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self.specials += Instance("IDELAYCTRL",
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self.specials += Instance("IDELAYCTRL",
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p_SIM_DEVICE="ULTRASCALE",
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p_SIM_DEVICE = "ULTRASCALE",
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i_REFCLK=cd.clk,
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i_REFCLK = cd.clk,
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i_RST=ic_reset)
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i_RST = ic_reset
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)
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# Lattice / iCE40 ----------------------------------------------------------------------------------
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# Lattice / iCE40 ----------------------------------------------------------------------------------
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@ -403,14 +404,14 @@ class iCE40PLL(Module):
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vco_freq_range = (533e6, 1066e6)
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vco_freq_range = (533e6, 1066e6)
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def __init__(self):
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def __init__(self):
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self.reset = Signal()
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self.reset = Signal()
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self.locked = Signal()
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self.locked = Signal()
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self.clkin_freq = None
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self.clkin_freq = None
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self.vcxo_freq = None
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self.vcxo_freq = None
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self.nclkouts = 0
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self.nclkouts = 0
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self.clkouts = {}
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self.clkouts = {}
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self.config = {}
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self.config = {}
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self.params = {}
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self.params = {}
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def register_clkin(self, clkin, freq):
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def register_clkin(self, clkin, freq):
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(clki_freq_min, clki_freq_max) = self.clki_freq_range
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(clki_freq_min, clki_freq_max) = self.clki_freq_range
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@ -469,16 +470,16 @@ class iCE40PLL(Module):
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filter_range = v
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filter_range = v
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break
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break
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self.params.update(
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self.params.update(
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p_FEEDBACK_PATH="SIMPLE",
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p_FEEDBACK_PATH = "SIMPLE",
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p_FILTER_RANGE=filter_range,
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p_FILTER_RANGE = filter_range,
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i_RESETB=~self.reset,
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i_RESETB = ~self.reset,
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i_REFERENCECLK=self.clkin,
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i_REFERENCECLK = self.clkin,
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o_LOCK=self.locked,
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o_LOCK = self.locked,
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)
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)
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for n, (clk, f, p, m) in sorted(self.clkouts.items()):
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for n, (clk, f, p, m) in sorted(self.clkouts.items()):
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self.params["p_DIVR"] = config["divr"]
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self.params["p_DIVR"] = config["divr"]
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self.params["p_DIVF"] = config["divf"]
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self.params["p_DIVF"] = config["divf"]
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self.params["p_DIVQ"] = config["divq"]
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self.params["p_DIVQ"] = config["divq"]
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self.params["o_PLLOUTGLOBAL"] = clk
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self.params["o_PLLOUTGLOBAL"] = clk
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self.specials += Instance("SB_PLL40_CORE", **self.params)
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self.specials += Instance("SB_PLL40_CORE", **self.params)
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@ -488,7 +489,7 @@ class iCE40PLL(Module):
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# - add proper phase support.
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# - add proper phase support.
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class ECP5PLL(Module):
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class ECP5PLL(Module):
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nclkouts_max = 3
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nclkouts_max = 3
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clkfb_div_range = (1, 128+1)
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clkfb_div_range = (1, 128+1)
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clko_div_range = (1, 128+1)
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clko_div_range = (1, 128+1)
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clki_freq_range = ( 8e6, 400e6)
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clki_freq_range = ( 8e6, 400e6)
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@ -496,14 +497,14 @@ class ECP5PLL(Module):
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vco_freq_range = ( 550e6, 1250e6)
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vco_freq_range = ( 550e6, 1250e6)
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def __init__(self):
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def __init__(self):
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self.reset = Signal()
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self.reset = Signal()
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self.locked = Signal()
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self.locked = Signal()
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self.clkin_freq = None
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self.clkin_freq = None
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self.vcxo_freq = None
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self.vcxo_freq = None
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self.nclkouts = 0
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self.nclkouts = 0
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self.clkouts = {}
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self.clkouts = {}
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self.config = {}
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self.config = {}
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self.params = {}
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self.params = {}
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def register_clkin(self, clkin, freq):
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def register_clkin(self, clkin, freq):
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(clki_freq_min, clki_freq_max) = self.clki_freq_range
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(clki_freq_min, clki_freq_max) = self.clki_freq_range
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@ -565,12 +566,12 @@ class ECP5PLL(Module):
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("MFG_GMCREF_SEL", "2")],
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("MFG_GMCREF_SEL", "2")],
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i_RST=self.reset,
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i_RST=self.reset,
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i_CLKI=self.clkin,
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i_CLKI = self.clkin,
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o_LOCK=self.locked,
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o_LOCK = self.locked,
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p_FEEDBK_PATH="INT_OS3", # CLKOS3 reserved for
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p_FEEDBK_PATH = "INT_OS3", # CLKOS3 reserved for
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p_CLKOS3_ENABLE="ENABLED", # feedback with div=1.
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p_CLKOS3_ENABLE = "ENABLED", # feedback with div=1.
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p_CLKOS3_DIV=1,
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p_CLKOS3_DIV = 1,
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p_CLKFB_DIV=config["clkfb_div"],
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p_CLKFB_DIV=config["clkfb_div"],
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p_CLKI_DIV=1,
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p_CLKI_DIV=1,
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@ -578,8 +579,8 @@ class ECP5PLL(Module):
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for n, (clk, f, p, m) in sorted(self.clkouts.items()):
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for n, (clk, f, p, m) in sorted(self.clkouts.items()):
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n_to_l = {0: "P", 1: "S", 2: "S2"}
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n_to_l = {0: "P", 1: "S", 2: "S2"}
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self.params["p_CLKO{}_ENABLE".format(n_to_l[n])] = "ENABLED"
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self.params["p_CLKO{}_ENABLE".format(n_to_l[n])] = "ENABLED"
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self.params["p_CLKO{}_DIV".format(n_to_l[n])] = config["clko{}_div".format(n)]
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self.params["p_CLKO{}_DIV".format(n_to_l[n])] = config["clko{}_div".format(n)]
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self.params["p_CLKO{}_FPHASE".format(n_to_l[n])] = 0
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self.params["p_CLKO{}_FPHASE".format(n_to_l[n])] = 0
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self.params["p_CLKO{}_CPHASE".format(n_to_l[n])] = p
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self.params["p_CLKO{}_CPHASE".format(n_to_l[n])] = p
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self.params["o_CLKO{}".format(n_to_l[n])] = clk
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self.params["o_CLKO{}".format(n_to_l[n])] = clk
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self.specials += Instance("EHXPLLL", **self.params)
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self.specials += Instance("EHXPLLL", **self.params)
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