soc/cores/clocks: improve readibility

2019-09-29 15:58:22 +02:00 · 2019-09-29 15:58:22 +02:00 · c6fe3f3145
parent 6fcb12a98f
commit c6fe3f3145
1 changed files with 84 additions and 83 deletions
--- a/litex/soc/cores/clock.py
+++ b/litex/soc/cores/clock.py
@ -385,7 +385,8 @@ class USIDELAYCTRL(Module):
        self.specials += Instance("IDELAYCTRL",
            p_SIM_DEVICE = "ULTRASCALE",
            i_REFCLK     = cd.clk,
-            i_RST=ic_reset)
+            i_RST        = ic_reset
+        )

 # Lattice / iCE40 ----------------------------------------------------------------------------------