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actorlib/spi/SingleGenerator: use CSR alignment bits

This commit is contained in:
Sebastien Bourdeauducq 2013-04-30 18:54:47 +02:00
parent dc0304a87b
commit c70c71502e
1 changed files with 7 additions and 6 deletions
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13
migen/actorlib/spi.py
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@ -40,9 +40,10 @@ def _create_csrs_assign(layout, target, atomic, prefix=""):
alignment = element[3]
else:
alignment = 0
reg = CSRStorage(nbits + alignment, reset=reset, atomic_write=atomic, name=prefix + name)
reg = CSRStorage(nbits + alignment, reset=reset, atomic_write=atomic,
alignment_bits=alignment, name=prefix + name)
csrs.append(reg)
assigns.append(getattr(target, name).eq(reg.storage[alignment:]))
assigns.append(getattr(target, name).eq(reg.storage))
return csrs, assigns
(MODE_EXTERNAL, MODE_SINGLE_SHOT, MODE_CONTINUOUS) = range(3)
@ -51,10 +52,10 @@ class SingleGenerator(Module):
def __init__(self, layout, mode):
self.source = Source(_convert_layout(layout))
self.busy = Signal()
self._csrs, assigns = _create_csrs_assign(layout, self.source.payload,
mode != MODE_SINGLE_SHOT)
self._csrs, assigns = _create_csrs_assign(layout, self.source.payload, mode != MODE_SINGLE_SHOT)
if mode == MODE_EXTERNAL:
trigger = self.trigger = Signal()
self.trigger = Signal()
trigger = self.trigger
elif mode == MODE_SINGLE_SHOT:
shoot = CSR()
self._csrs.insert(0, shoot)
@ -67,7 +68,7 @@ class SingleGenerator(Module):
raise ValueError
self.comb += self.busy.eq(self.source.stb)
stmts = [self.source.stb.eq(trigger)] + assigns
self.sync += [If(self.source.ack | ~self.source.stb, *stmts)]
self.sync += If(self.source.ack | ~self.source.stb, *stmts)
def get_csrs(self):
return self._csrs