examples/de1: use of MigIo
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@ -1,5 +1,5 @@
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class Constraints:
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def __init__(self, in_clk, in_rst_n, spi2csr0, led0):
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def __init__(self, in_clk, in_rst_n, spi2csr0, led0, sw0):
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self.constraints = []
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def add(signal, pin, vec=-1, iostandard="3.3-V LVTTL", extra="", sch=""):
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self.constraints.append((signal, vec, pin, iostandard, extra,sch))
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@ -24,6 +24,9 @@ class Constraints:
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# led0
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add_vec(led0, ["U22", "U21", "V22", "V21",
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"W22" , "W21" , "Y22" , "Y21"])
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# sw0
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add_vec(sw0, ["L22", "L21", "M22", "V12",
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"W12" , "U12" , "U11" , "M2"])
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def get_ios(self):
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return set([c[0] for c in self.constraints])
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@ -42,7 +42,7 @@ from migen.bank.description import *
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import sys
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sys.path.append("../../")
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from migScope import trigger, recorder
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from migScope import trigger, recorder, migIo
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import spi2Csr
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from timings import *
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@ -74,10 +74,8 @@ RECORDER_ADDR = 0x0400
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#==============================================================================
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def get():
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# Control Reg
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control_reg0 = RegisterField("control_reg0", 32, reset=0, access_dev=READ_ONLY)
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regs = [control_reg0]
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bank0 = csrgen.Bank(regs,address=CONTROL_ADDR)
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# migIo
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migIo0 = migIo.MigIo(8,"IO")
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# Trigger
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term0 = trigger.Term(trig_width)
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@ -92,7 +90,7 @@ def get():
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# Csr Interconnect
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csrcon0 = csr.Interconnect(spi2csr0.csr,
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[
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bank0.interface,
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migIo0.bank.interface,
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trigger0.bank.interface,
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recorder0.bank.interface
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])
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@ -107,10 +105,11 @@ def get():
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# Led
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led0 = Signal(BV(8))
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comb += [
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led0.eq(control_reg0.field.r[:8])
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]
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comb += [led0.eq(migIo0.o)]
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#Switch
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sw0 = Signal(BV(8))
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comb += [migIo0.i.eq(sw0)]
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# Dat / Trig Bus
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@ -135,7 +134,7 @@ def get():
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]
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frag = autofragment.from_local()
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frag += Fragment(sync=sync,comb=comb)
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cst = Constraints(in_clk, in_rst_n, spi2csr0, led0)
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cst = Constraints(in_clk, in_rst_n, spi2csr0, led0, sw0)
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src_verilog, vns = verilog.convert(frag,
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cst.get_ios(),
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name="de1",
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